#include "SPUSubtarget.h"
#include "SPU.h"
#include "SPURegisterInfo.h"
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/SmallVector.h"
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "SPUGenSubtargetInfo.inc"
using namespace llvm;
SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS) :
SPUGenSubtargetInfo(TT, CPU, FS),
StackAlignment(16),
ProcDirective(SPU::DEFAULT_PROC),
UseLargeMem(false)
{
std::string default_cpu("v0");
ParseSubtargetFeatures(default_cpu, FS);
InstrItins = getInstrItineraryForCPU(default_cpu);
}
void SPUSubtarget::SetJITMode() {
}
bool SPUSubtarget::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
CriticalPathRCs.clear();
CriticalPathRCs.push_back(&SPU::R8CRegClass);
CriticalPathRCs.push_back(&SPU::R16CRegClass);
CriticalPathRCs.push_back(&SPU::R32CRegClass);
CriticalPathRCs.push_back(&SPU::R32FPRegClass);
CriticalPathRCs.push_back(&SPU::R64CRegClass);
CriticalPathRCs.push_back(&SPU::VECREGRegClass);
return OptLevel >= CodeGenOpt::Default;
}