:function:::void:check_mdmx:instruction_word insn
*sb1:
{
if (!COP_Usable(1))
SignalExceptionCoProcessorUnusable(1);
if ((SR & status_MX) == 0)
SignalExceptionMDMX();
check_u64 (SD_, insn);
}
:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
*sb1:
{
switch (fmtsel & 0x03)
{
case 0x00:
case 0x02:
return 1;
case 0x01:
case 0x03:
SignalException (ReservedInstruction, insn);
return 0;
}
return 0;
}
:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
*sb1:
{
switch (fmtop & 0x01)
{
case 0x00:
return 1;
case 0x01:
SignalException (ReservedInstruction, insn);
return 0;
}
return 0;
}
011110,10,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.sb1.fmt
"rach.?<X>.%s<FMTOP> v<VD>"
*sb1:
{
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
}
011110,00,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.sb1.fmt
"racl.?<X>.%s<FMTOP> v<VD>"
*sb1:
{
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
}
011110,01,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.sb1.fmt
"racm.?<X>.%s<FMTOP> v<VD>"
*sb1:
{
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
}
011110,2.X1!0!1!2,2.X2,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RAC.sb1.fmt
"rac?<X1>.?<X2> v<VD>"
*sb1:
{
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
}
011110,10,2.X!0,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.sb1.fmt
"wach.?<X>.%s<FMTOP> v<VS>"
*sb1:
{
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
}
011110,00,2.X!0,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.sb1.fmt
"wacl.?<X>.%s<FMTOP> v<VS>,v<VT>"
*sb1:
{
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
}
011110,2.X1!0!2,2.X2,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WAC.sb1.fmt
"wacl?<X1>.?<X2>.%s<FMTOP> v<VS>,v<VT>"
*sb1:
{
check_mdmx (SD_, instruction_0);
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
}
011110,5.FMTSEL,5.VT,5.VS,5.VD,001001:MDMX:64::PABSDIFF.fmt
"pabsdiff.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
*sb1:
{
check_mdmx (SD_, instruction_0);
if (SR & status_SBX)
{
check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
}
else
SignalException(ReservedInstruction, instruction_0);
}
011110,5.FMTSEL,5.VT,5.VS,00000,110101:MDMX:64::PABSDIFC.fmt
"pabsdifc.%<FMTSEL> v<VS>,v<VT>"
*sb1:
{
check_mdmx (SD_, instruction_0);
if (SR & status_SBX)
{
check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
}
else
SignalException(ReservedInstruction, instruction_0);
}
011110,5.FMTSEL,5.VT,5.VS,5.VD,001000:MDMX:64::PAVG.fmt
"pavg.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
*sb1:
{
check_mdmx (SD_, instruction_0);
if (SR & status_SBX)
{
check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
}
else
SignalException(ReservedInstruction, instruction_0);
}