#define WANT_CPU sh64
#define WANT_CPU_SH64
#include "sim-main.h"
#include "cgen-ops.h"
UDI
sh64_h_pc_get (SIM_CPU *current_cpu)
{
return GET_H_PC ();
}
void
sh64_h_pc_set (SIM_CPU *current_cpu, UDI newval)
{
SET_H_PC (newval);
}
DI
sh64_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_GR (regno);
}
void
sh64_h_gr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_GR (regno, newval);
}
SI
sh64_h_grc_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_GRC (regno);
}
void
sh64_h_grc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
SET_H_GRC (regno, newval);
}
DI
sh64_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_CR (regno);
}
void
sh64_h_cr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_CR (regno, newval);
}
SI
sh64_h_sr_get (SIM_CPU *current_cpu)
{
return CPU (h_sr);
}
void
sh64_h_sr_set (SIM_CPU *current_cpu, SI newval)
{
CPU (h_sr) = newval;
}
SI
sh64_h_fpscr_get (SIM_CPU *current_cpu)
{
return CPU (h_fpscr);
}
void
sh64_h_fpscr_set (SIM_CPU *current_cpu, SI newval)
{
CPU (h_fpscr) = newval;
}
BI
sh64_h_frbit_get (SIM_CPU *current_cpu)
{
return GET_H_FRBIT ();
}
void
sh64_h_frbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_FRBIT (newval);
}
BI
sh64_h_szbit_get (SIM_CPU *current_cpu)
{
return GET_H_SZBIT ();
}
void
sh64_h_szbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_SZBIT (newval);
}
BI
sh64_h_prbit_get (SIM_CPU *current_cpu)
{
return GET_H_PRBIT ();
}
void
sh64_h_prbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_PRBIT (newval);
}
BI
sh64_h_sbit_get (SIM_CPU *current_cpu)
{
return GET_H_SBIT ();
}
void
sh64_h_sbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_SBIT (newval);
}
BI
sh64_h_mbit_get (SIM_CPU *current_cpu)
{
return GET_H_MBIT ();
}
void
sh64_h_mbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_MBIT (newval);
}
BI
sh64_h_qbit_get (SIM_CPU *current_cpu)
{
return GET_H_QBIT ();
}
void
sh64_h_qbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_QBIT (newval);
}
SF
sh64_h_fr_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_fr[regno]);
}
void
sh64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
CPU (h_fr[regno]) = newval;
}
DF
sh64_h_fp_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_fp[regno]);
}
void
sh64_h_fp_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
CPU (h_fp[regno]) = newval;
}
SF
sh64_h_fv_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FV (regno);
}
void
sh64_h_fv_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FV (regno, newval);
}
SF
sh64_h_fmtx_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FMTX (regno);
}
void
sh64_h_fmtx_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FMTX (regno, newval);
}
DF
sh64_h_dr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_DR (regno);
}
void
sh64_h_dr_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_DR (regno, newval);
}
DI
sh64_h_tr_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_tr[regno]);
}
void
sh64_h_tr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
CPU (h_tr[regno]) = newval;
}
BI
sh64_h_endian_get (SIM_CPU *current_cpu)
{
return GET_H_ENDIAN ();
}
void
sh64_h_endian_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_ENDIAN (newval);
}
BI
sh64_h_ism_get (SIM_CPU *current_cpu)
{
return GET_H_ISM ();
}
void
sh64_h_ism_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_ISM (newval);
}
SF
sh64_h_frc_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FRC (regno);
}
void
sh64_h_frc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FRC (regno, newval);
}
DF
sh64_h_drc_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_DRC (regno);
}
void
sh64_h_drc_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_DRC (regno, newval);
}
SF
sh64_h_xf_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_XF (regno);
}
void
sh64_h_xf_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_XF (regno, newval);
}
DF
sh64_h_xd_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_XD (regno);
}
void
sh64_h_xd_set (SIM_CPU *current_cpu, UINT regno, DF newval)
{
SET_H_XD (regno, newval);
}
SF
sh64_h_fvc_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_FVC (regno);
}
void
sh64_h_fvc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
{
SET_H_FVC (regno, newval);
}
SI
sh64_h_fpccr_get (SIM_CPU *current_cpu)
{
return GET_H_FPCCR ();
}
void
sh64_h_fpccr_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_FPCCR (newval);
}
SI
sh64_h_gbr_get (SIM_CPU *current_cpu)
{
return GET_H_GBR ();
}
void
sh64_h_gbr_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_GBR (newval);
}
SI
sh64_h_pr_get (SIM_CPU *current_cpu)
{
return GET_H_PR ();
}
void
sh64_h_pr_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_PR (newval);
}
SI
sh64_h_macl_get (SIM_CPU *current_cpu)
{
return GET_H_MACL ();
}
void
sh64_h_macl_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_MACL (newval);
}
SI
sh64_h_mach_get (SIM_CPU *current_cpu)
{
return GET_H_MACH ();
}
void
sh64_h_mach_set (SIM_CPU *current_cpu, SI newval)
{
SET_H_MACH (newval);
}
BI
sh64_h_tbit_get (SIM_CPU *current_cpu)
{
return GET_H_TBIT ();
}
void
sh64_h_tbit_set (SIM_CPU *current_cpu, BI newval)
{
SET_H_TBIT (newval);
}
void
sh64_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
int *indices, TRACE_RECORD *tr)
{
}