#ifndef M32R_SIM_H
#define M32R_SIM_H
#define PSW_REGNUM 16
#define CBR_REGNUM 17
#define SPI_REGNUM 18
#define SPU_REGNUM 19
#define BPC_REGNUM 20
#define PC_REGNUM 21
#define ACCL_REGNUM 22
#define ACCH_REGNUM 23
#define ACC1L_REGNUM 24
#define ACC1H_REGNUM 25
#define BBPSW_REGNUM 26
#define BBPC_REGNUM 27
extern int m32r_decode_gdb_ctrl_regnum (int);
#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
extern USI m32rxf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rxf_h_cr_set_handler (SIM_CPU *, UINT, USI);
extern UQI m32rxf_h_psw_get_handler (SIM_CPU *);
extern void m32rxf_h_psw_set_handler (SIM_CPU *, UQI);
extern DI m32rxf_h_accum_get_handler (SIM_CPU *);
extern void m32rxf_h_accum_set_handler (SIM_CPU *, DI);
extern DI m32rxf_h_accums_get_handler (SIM_CPU *, UINT);
extern void m32rxf_h_accums_set_handler (SIM_CPU *, UINT, DI);
typedef struct {
unsigned int fillnop_count;
unsigned int parallel_count;
unsigned int short_count;
unsigned int long_count;
unsigned long insn_cycles;
unsigned long cti_stall;
unsigned long load_stall;
unsigned long biggest_cycles;
unsigned int load_regs;
unsigned int load_regs_pending;
} M32R_MISC_PROFILE;
void m32r_init_insn_cycles (SIM_CPU *, int);
void m32r_record_insn_cycles (SIM_CPU *, int);
#define PROFILE_COUNT_FILLNOPS(cpu, addr) \
do { \
if (PROFILE_INSN_P (cpu) \
&& (addr & 3) != 0) \
++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
} while (0)
#define PROFILE_COUNT_PARINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
} while (0)
#define PROFILE_COUNT_SHORTINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
} while (0)
#define PROFILE_COUNT_LONGINSNS(cpu) \
do { \
if (PROFILE_INSN_P (cpu)) \
++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
} while (0)
#define GETTWI GETTSI
#define SETTWI SETTSI
#define NEW_PC_BASE 0xffff0001
#define NEW_PC_SKIP NEW_PC_BASE
#define NEW_PC_2 (NEW_PC_BASE + 2)
#define NEW_PC_4 (NEW_PC_BASE + 4)
#define NEW_PC_BRANCH_P(addr) (((addr) & 1) == 0)
#if defined (WANT_CPU_M32RXF) && ! WITH_SCACHE_PBB_M32RXF
#undef SEM_NEXT_VPC
#define SEM_NEXT_VPC(abuf, len) (NEW_PC_BASE + (len))
#undef SEM_SKIP_INSN
#define SEM_SKIP_INSN(cpu, sc, vpcvar, yes) FIXME
#endif
#define EIT_SYSBREAK_ADDR 0x10
#define EIT_RSVD_INSN_ADDR 0x20
#define EIT_ADDR_EXCP_ADDR 0x30
#define EIT_TRAP_BASE_ADDR 0x40
#define EIT_EXTERN_ADDR 0x80
#define EIT_RESET_ADDR 0x7ffffff0
#define EIT_WAKEUP_ADDR 0x7ffffff0
#define TRAP_SYSCALL 0
#define TRAP_BREAKPOINT 1
#define MSPR_ADDR 0xfffffff7
#define MSPR_PURGE 1
#define MLCR_ADDR 0xfffffff7
#define MLCR_LM 1
#define MPMR_ADDR 0xfffffffb
#define MCCR_ADDR 0xffffffff
#define MCCR_CP 0x80
#define MCCR_CM0 2
#define MCCR_CM1 1
#ifdef M32R_EVA
#define UART_INCHAR_ADDR 0xff102013
#define UART_OUTCHAR_ADDR 0xff10200f
#define UART_STATUS_ADDR 0xff102006
#define UART_INPUT_READY0
#else
#define UART_INCHAR_ADDR 0xff004009
#define UART_OUTCHAR_ADDR 0xff004007
#define UART_STATUS_ADDR 0xff004002
#endif
#define UART_INPUT_READY 0x4
#define UART_OUTPUT_READY 0x1
#define M32R_DEVICE_ADDR 0xff000000
#define M32R_DEVICE_LEN 0x01000000
extern device m32r_devices;
struct _device { int foo; };
USI m32r_trap (SIM_CPU *, PCADDR, int);
#endif