#ifndef CPU_M32RXF_H
#define CPU_M32RXF_H
#define MAX_LIW_INSNS 2
#define MAX_PARALLEL_INSNS 2
typedef struct {
struct {
USI h_pc;
#define GET_H_PC() CPU (h_pc)
#define SET_H_PC(x) (CPU (h_pc) = (x))
SI h_gr[16];
#define GET_H_GR(a1) CPU (h_gr)[a1]
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
USI h_cr[16];
#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
#define SET_H_CR(index, x) \
do { \
m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
;} while (0)
DI h_accum;
#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
#define SET_H_ACCUM(x) \
do { \
m32rxf_h_accum_set_handler (current_cpu, (x));\
;} while (0)
DI h_accums[2];
#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
#define SET_H_ACCUMS(index, x) \
do { \
m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
;} while (0)
BI h_cond;
#define GET_H_COND() CPU (h_cond)
#define SET_H_COND(x) (CPU (h_cond) = (x))
UQI h_psw;
#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
#define SET_H_PSW(x) \
do { \
m32rxf_h_psw_set_handler (current_cpu, (x));\
;} while (0)
UQI h_bpsw;
#define GET_H_BPSW() CPU (h_bpsw)
#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
UQI h_bbpsw;
#define GET_H_BBPSW() CPU (h_bbpsw)
#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
BI h_lock;
#define GET_H_LOCK() CPU (h_lock)
#define SET_H_LOCK(x) (CPU (h_lock) = (x))
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} M32RXF_CPU_DATA;
USI m32rxf_h_pc_get (SIM_CPU *);
void m32rxf_h_pc_set (SIM_CPU *, USI);
SI m32rxf_h_gr_get (SIM_CPU *, UINT);
void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
USI m32rxf_h_cr_get (SIM_CPU *, UINT);
void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
DI m32rxf_h_accum_get (SIM_CPU *);
void m32rxf_h_accum_set (SIM_CPU *, DI);
DI m32rxf_h_accums_get (SIM_CPU *, UINT);
void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
BI m32rxf_h_cond_get (SIM_CPU *);
void m32rxf_h_cond_set (SIM_CPU *, BI);
UQI m32rxf_h_psw_get (SIM_CPU *);
void m32rxf_h_psw_set (SIM_CPU *, UQI);
UQI m32rxf_h_bpsw_get (SIM_CPU *);
void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
UQI m32rxf_h_bbpsw_get (SIM_CPU *);
void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
BI m32rxf_h_lock_get (SIM_CPU *);
void m32rxf_h_lock_set (SIM_CPU *, BI);
extern CPUREG_FETCH_FN m32rxf_fetch_register;
extern CPUREG_STORE_FN m32rxf_store_register;
typedef struct {
int empty;
} MODEL_M32RX_DATA;
union sem_fields {
struct {
int empty;
} fmt_empty;
struct {
UINT f_uimm4;
} sfmt_trap;
struct {
IADDR i_disp24;
unsigned char out_h_gr_SI_14;
} sfmt_bl24;
struct {
IADDR i_disp8;
unsigned char out_h_gr_SI_14;
} sfmt_bl8;
struct {
SI f_imm1;
UINT f_accd;
UINT f_accs;
} sfmt_rac_dsi;
struct {
SI* i_dr;
UINT f_hi16;
UINT f_r1;
unsigned char out_dr;
} sfmt_seth;
struct {
SI* i_src1;
UINT f_accs;
UINT f_r1;
unsigned char in_src1;
} sfmt_mvtachi_a;
struct {
SI* i_dr;
UINT f_accs;
UINT f_r1;
unsigned char out_dr;
} sfmt_mvfachi_a;
struct {
ADDR i_uimm24;
SI* i_dr;
UINT f_r1;
unsigned char out_dr;
} sfmt_ld24;
struct {
SI* i_sr;
UINT f_r2;
unsigned char in_sr;
unsigned char out_h_gr_SI_14;
} sfmt_jl;
struct {
SI* i_dr;
UINT f_r1;
UINT f_uimm5;
unsigned char in_dr;
unsigned char out_dr;
} sfmt_slli;
struct {
SI* i_dr;
INT f_simm8;
UINT f_r1;
unsigned char in_dr;
unsigned char out_dr;
} sfmt_addi;
struct {
SI* i_src1;
SI* i_src2;
UINT f_r1;
UINT f_r2;
unsigned char in_src1;
unsigned char in_src2;
unsigned char out_src2;
} sfmt_st_plus;
struct {
SI* i_src1;
SI* i_src2;
INT f_simm16;
UINT f_r1;
UINT f_r2;
unsigned char in_src1;
unsigned char in_src2;
} sfmt_st_d;
struct {
SI* i_src1;
SI* i_src2;
UINT f_acc;
UINT f_r1;
UINT f_r2;
unsigned char in_src1;
unsigned char in_src2;
} sfmt_machi_a;
struct {
SI* i_dr;
SI* i_sr;
UINT f_r1;
UINT f_r2;
unsigned char in_sr;
unsigned char out_dr;
unsigned char out_sr;
} sfmt_ld_plus;
struct {
IADDR i_disp16;
SI* i_src1;
SI* i_src2;
UINT f_r1;
UINT f_r2;
unsigned char in_src1;
unsigned char in_src2;
} sfmt_beq;
struct {
SI* i_dr;
SI* i_sr;
UINT f_r1;
UINT f_r2;
UINT f_uimm16;
unsigned char in_sr;
unsigned char out_dr;
} sfmt_and3;
struct {
SI* i_dr;
SI* i_sr;
INT f_simm16;
UINT f_r1;
UINT f_r2;
unsigned char in_sr;
unsigned char out_dr;
} sfmt_add3;
struct {
SI* i_dr;
SI* i_sr;
UINT f_r1;
UINT f_r2;
unsigned char in_dr;
unsigned char in_sr;
unsigned char out_dr;
} sfmt_add;
#if WITH_SCACHE_PBB
struct {
const struct argbuf *abuf;
} write;
struct {
int first_p;
} before;
struct {
int empty;
} after;
struct {
int insn_count;
SCACHE *next;
SCACHE *branch_target;
} chain;
#endif
};
struct argbuf {
IADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
char skip_count;
char unused;
union sem semantic;
int written;
union sem_fields fields;
};
struct scache {
struct argbuf argbuf;
};
#define EXTRACT_IFMT_EMPTY_VARS \
unsigned int length;
#define EXTRACT_IFMT_EMPTY_CODE \
length = 0; \
#define EXTRACT_IFMT_ADD_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_ADD_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_ADD3_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_ADD3_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_AND3_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
#define EXTRACT_IFMT_AND3_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_OR3_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
#define EXTRACT_IFMT_OR3_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_ADDI_VARS \
UINT f_op1; \
UINT f_r1; \
INT f_simm8; \
unsigned int length;
#define EXTRACT_IFMT_ADDI_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
#define EXTRACT_IFMT_ADDV3_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_ADDV3_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_BC8_VARS \
UINT f_op1; \
UINT f_r1; \
SI f_disp8; \
unsigned int length;
#define EXTRACT_IFMT_BC8_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
UINT f_r1; \
SI f_disp24; \
unsigned int length;
#define EXTRACT_IFMT_BC24_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
SI f_disp16; \
unsigned int length;
#define EXTRACT_IFMT_BEQ_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
SI f_disp16; \
unsigned int length;
#define EXTRACT_IFMT_BEQZ_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_CMP_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_CMPI_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_CMPI_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_CMPZ_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_CMPZ_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_DIV_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_DIV_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_JC_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_JC_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_LD24_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_uimm24; \
unsigned int length;
#define EXTRACT_IFMT_LD24_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
#define EXTRACT_IFMT_LDI16_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_LDI16_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_MACHI_A_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_acc; \
UINT f_op23; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_MACHI_A_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_MVFACHI_A_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_accs; \
UINT f_op3; \
unsigned int length;
#define EXTRACT_IFMT_MVFACHI_A_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
#define EXTRACT_IFMT_MVFC_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_MVFC_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_MVTACHI_A_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_accs; \
UINT f_op3; \
unsigned int length;
#define EXTRACT_IFMT_MVTACHI_A_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
#define EXTRACT_IFMT_MVTC_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_MVTC_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_NOP_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
unsigned int length;
#define EXTRACT_IFMT_NOP_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_RAC_DSI_VARS \
UINT f_op1; \
UINT f_accd; \
UINT f_bits67; \
UINT f_op2; \
UINT f_accs; \
UINT f_bit14; \
SI f_imm1; \
unsigned int length;
#define EXTRACT_IFMT_RAC_DSI_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
#define EXTRACT_IFMT_SETH_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
UINT f_hi16; \
unsigned int length;
#define EXTRACT_IFMT_SETH_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_SLLI_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_shift_op2; \
UINT f_uimm5; \
unsigned int length;
#define EXTRACT_IFMT_SLLI_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
#define EXTRACT_IFMT_ST_D_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_ST_D_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
#define EXTRACT_IFMT_TRAP_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_uimm4; \
unsigned int length;
#define EXTRACT_IFMT_TRAP_CODE \
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
#define EXTRACT_IFMT_SATB_VARS \
UINT f_op1; \
UINT f_r1; \
UINT f_op2; \
UINT f_r2; \
UINT f_uimm16; \
unsigned int length;
#define EXTRACT_IFMT_SATB_CODE \
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
struct parexec {
union {
struct {
int empty;
} sfmt_empty;
struct {
SI dr;
} sfmt_add;
struct {
SI dr;
} sfmt_add3;
struct {
SI dr;
} sfmt_and3;
struct {
SI dr;
} sfmt_or3;
struct {
SI dr;
} sfmt_addi;
struct {
BI condbit;
SI dr;
} sfmt_addv;
struct {
BI condbit;
SI dr;
} sfmt_addv3;
struct {
BI condbit;
SI dr;
} sfmt_addx;
struct {
USI pc;
} sfmt_bc8;
struct {
USI pc;
} sfmt_bc24;
struct {
USI pc;
} sfmt_beq;
struct {
USI pc;
} sfmt_beqz;
struct {
SI h_gr_SI_14;
USI pc;
} sfmt_bl8;
struct {
SI h_gr_SI_14;
USI pc;
} sfmt_bl24;
struct {
SI h_gr_SI_14;
USI pc;
} sfmt_bcl8;
struct {
SI h_gr_SI_14;
USI pc;
} sfmt_bcl24;
struct {
USI pc;
} sfmt_bra8;
struct {
USI pc;
} sfmt_bra24;
struct {
BI condbit;
} sfmt_cmp;
struct {
BI condbit;
} sfmt_cmpi;
struct {
BI condbit;
} sfmt_cmpz;
struct {
SI dr;
} sfmt_div;
struct {
USI pc;
} sfmt_jc;
struct {
SI h_gr_SI_14;
USI pc;
} sfmt_jl;
struct {
USI pc;
} sfmt_jmp;
struct {
SI dr;
} sfmt_ld;
struct {
SI dr;
} sfmt_ld_d;
struct {
SI dr;
} sfmt_ldb;
struct {
SI dr;
} sfmt_ldb_d;
struct {
SI dr;
} sfmt_ldh;
struct {
SI dr;
} sfmt_ldh_d;
struct {
SI dr;
SI sr;
} sfmt_ld_plus;
struct {
SI dr;
} sfmt_ld24;
struct {
SI dr;
} sfmt_ldi8;
struct {
SI dr;
} sfmt_ldi16;
struct {
SI dr;
BI h_lock_BI;
} sfmt_lock;
struct {
DI acc;
} sfmt_machi_a;
struct {
DI acc;
} sfmt_mulhi_a;
struct {
SI dr;
} sfmt_mv;
struct {
SI dr;
} sfmt_mvfachi_a;
struct {
SI dr;
} sfmt_mvfc;
struct {
DI accs;
} sfmt_mvtachi_a;
struct {
USI dcr;
} sfmt_mvtc;
struct {
int empty;
} sfmt_nop;
struct {
DI accd;
} sfmt_rac_dsi;
struct {
UQI h_bpsw_UQI;
USI h_cr_USI_6;
UQI h_psw_UQI;
USI pc;
} sfmt_rte;
struct {
SI dr;
} sfmt_seth;
struct {
SI dr;
} sfmt_sll3;
struct {
SI dr;
} sfmt_slli;
struct {
SI h_memory_SI_src2;
USI h_memory_SI_src2_idx;
} sfmt_st;
struct {
SI h_memory_SI_add__DFLT_src2_slo16;
USI h_memory_SI_add__DFLT_src2_slo16_idx;
} sfmt_st_d;
struct {
QI h_memory_QI_src2;
USI h_memory_QI_src2_idx;
} sfmt_stb;
struct {
QI h_memory_QI_add__DFLT_src2_slo16;
USI h_memory_QI_add__DFLT_src2_slo16_idx;
} sfmt_stb_d;
struct {
HI h_memory_HI_src2;
USI h_memory_HI_src2_idx;
} sfmt_sth;
struct {
HI h_memory_HI_add__DFLT_src2_slo16;
USI h_memory_HI_add__DFLT_src2_slo16_idx;
} sfmt_sth_d;
struct {
SI h_memory_SI_new_src2;
USI h_memory_SI_new_src2_idx;
SI src2;
} sfmt_st_plus;
struct {
UQI h_bbpsw_UQI;
UQI h_bpsw_UQI;
USI h_cr_USI_14;
USI h_cr_USI_6;
UQI h_psw_UQI;
SI pc;
} sfmt_trap;
struct {
BI h_lock_BI;
SI h_memory_SI_src2;
USI h_memory_SI_src2_idx;
} sfmt_unlock;
struct {
SI dr;
} sfmt_satb;
struct {
SI dr;
} sfmt_sat;
struct {
DI h_accums_DI_0;
} sfmt_sadd;
struct {
DI h_accums_DI_1;
} sfmt_macwu1;
struct {
DI accum;
} sfmt_msblo;
struct {
DI h_accums_DI_1;
} sfmt_mulwu1;
struct {
int empty;
} sfmt_sc;
} operands;
int written;
};
typedef struct trace_record {
IADDR pc;
} TRACE_RECORD;
#endif