#include "defs.h"
#include "arch-utils.h"
#include "block.h"
#include "dummy-frame.h"
#include "frame.h"
#include "frame-base.h"
#include "frame-unwind.h"
#include "inferior.h"
#include "gdbcmd.h"
#include "gdbcore.h"
#include "objfiles.h"
#include "regcache.h"
#include "regset.h"
#include "symfile.h"
#include "complaints.h"
#include "gdb_assert.h"
#include "amd64-tdep.h"
#include "i387-tdep.h"
#include "x86-shared-tdep.h"
struct amd64_register_info
{
char *name;
struct type **type;
};
static struct type *amd64_sse_type = NULL;
static struct amd64_register_info const amd64_register_info[] =
{
{ "rax", &builtin_type_int64 },
{ "rbx", &builtin_type_int64 },
{ "rcx", &builtin_type_int64 },
{ "rdx", &builtin_type_int64 },
{ "rsi", &builtin_type_int64 },
{ "rdi", &builtin_type_int64 },
{ "rbp", &builtin_type_void_data_ptr },
{ "rsp", &builtin_type_void_data_ptr },
{ "r8", &builtin_type_int64 },
{ "r9", &builtin_type_int64 },
{ "r10", &builtin_type_int64 },
{ "r11", &builtin_type_int64 },
{ "r12", &builtin_type_int64 },
{ "r13", &builtin_type_int64 },
{ "r14", &builtin_type_int64 },
{ "r15", &builtin_type_int64 },
{ "rip", &builtin_type_void_func_ptr },
{ "eflags", &builtin_type_int32 },
{ "cs", &builtin_type_int32 },
{ "ss", &builtin_type_int32 },
{ "ds", &builtin_type_int32 },
{ "es", &builtin_type_int32 },
{ "fs", &builtin_type_int32 },
{ "gs", &builtin_type_int32 },
{ "st0", &builtin_type_i387_ext },
{ "st1", &builtin_type_i387_ext },
{ "st2", &builtin_type_i387_ext },
{ "st3", &builtin_type_i387_ext },
{ "st4", &builtin_type_i387_ext },
{ "st5", &builtin_type_i387_ext },
{ "st6", &builtin_type_i387_ext },
{ "st7", &builtin_type_i387_ext },
{ "fctrl", &builtin_type_int32 },
{ "fstat", &builtin_type_int32 },
{ "ftag", &builtin_type_int32 },
{ "fiseg", &builtin_type_int32 },
{ "fioff", &builtin_type_int32 },
{ "foseg", &builtin_type_int32 },
{ "fooff", &builtin_type_int32 },
{ "fop", &builtin_type_int32 },
{ "xmm0", &amd64_sse_type },
{ "xmm1", &amd64_sse_type },
{ "xmm2", &amd64_sse_type },
{ "xmm3", &amd64_sse_type },
{ "xmm4", &amd64_sse_type },
{ "xmm5", &amd64_sse_type },
{ "xmm6", &amd64_sse_type },
{ "xmm7", &amd64_sse_type },
{ "xmm8", &amd64_sse_type },
{ "xmm9", &amd64_sse_type },
{ "xmm10", &amd64_sse_type },
{ "xmm11", &amd64_sse_type },
{ "xmm12", &amd64_sse_type },
{ "xmm13", &amd64_sse_type },
{ "xmm14", &amd64_sse_type },
{ "xmm15", &amd64_sse_type },
{ "mxcsr", &builtin_type_int32 }
};
#define AMD64_NUM_REGS \
(sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
static const char *
amd64_register_name (int regnum)
{
if (regnum >= 0 && regnum < AMD64_NUM_REGS)
return amd64_register_info[regnum].name;
return NULL;
}
static struct type *
amd64_register_type (struct gdbarch *gdbarch, int regnum)
{
gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS);
if (amd64_sse_type == NULL)
amd64_sse_type = build_builtin_type_vec128i_big ();
return *amd64_register_info[regnum].type;
}
static int amd64_dwarf_regmap[] =
{
AMD64_RAX_REGNUM, AMD64_RDX_REGNUM,
AMD64_RCX_REGNUM, AMD64_RBX_REGNUM,
AMD64_RSI_REGNUM, AMD64_RDI_REGNUM,
AMD64_RBP_REGNUM,
AMD64_RSP_REGNUM,
8, 9, 10, 11, 12, 13, 14, 15,
AMD64_RIP_REGNUM,
AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9,
AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11,
AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13,
AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15,
AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7
};
static const int amd64_dwarf_regmap_len =
(sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
static int
amd64_dwarf_reg_to_regnum (int reg)
{
int regnum = -1;
if (reg >= 0 && reg < amd64_dwarf_regmap_len)
regnum = amd64_dwarf_regmap[reg];
if (regnum == -1)
complaint (&symfile_complaints, _("Unmapped DWARF Register #%d encountered."), reg);
return regnum;
}
static void
swapped_regcache_raw_write_part (struct regcache *regcache, int regnum,
int offset, int len, const gdb_byte *buf)
{
int j;
gdb_byte swapper_buf[16];
if (regnum < AMD64_XMM0_REGNUM || regnum > AMD64_XMM0_REGNUM + 15)
{
regcache_raw_write_part (regcache, regnum, offset, len, buf);
return;
}
regcache_raw_read (regcache, regnum, swapper_buf);
for (j = 0; j < 8; j++)
{
gdb_byte tmp = swapper_buf[j];
swapper_buf[j] = swapper_buf[16 - j - 1];
swapper_buf[16 - j - 1] = tmp;
}
memcpy (&swapper_buf[offset], buf, len);
for (j = 0; j < 8; j++)
{
gdb_byte tmp = swapper_buf[j];
swapper_buf[j] = swapper_buf[16 - j - 1];
swapper_buf[16 - j - 1] = tmp;
}
regcache_raw_write (regcache, regnum, swapper_buf);
}
static void
swapped_regcache_raw_read_part (struct regcache *regcache, int regnum,
int offset, int len, gdb_byte *buf)
{
int j;
gdb_byte swapper_buf[16];
if (regnum < AMD64_XMM0_REGNUM || regnum > AMD64_XMM0_REGNUM + 15)
{
regcache_raw_read_part (regcache, regnum, offset, len, buf);
return;
}
regcache_raw_read (regcache, regnum, swapper_buf);
for (j = 0; j < 8; j++)
{
gdb_byte tmp = swapper_buf[j];
swapper_buf[j] = swapper_buf[16 - j - 1];
swapper_buf[16 - j - 1] = tmp;
}
memcpy (buf, &swapper_buf[offset], len);
}
static int
amd64_convert_register_p (int regnum, struct type *type)
{
return i386_fp_regnum_p (regnum);
}
enum amd64_reg_class
{
AMD64_INTEGER,
AMD64_SSE,
AMD64_SSEUP,
AMD64_X87,
AMD64_X87UP,
AMD64_COMPLEX_X87,
AMD64_NO_CLASS,
AMD64_MEMORY
};
static enum amd64_reg_class
amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
{
if (class1 == class2)
return class1;
if (class1 == AMD64_NO_CLASS)
return class2;
if (class2 == AMD64_NO_CLASS)
return class1;
if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
return AMD64_MEMORY;
if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
return AMD64_INTEGER;
if (class1 == AMD64_X87 || class1 == AMD64_X87UP
|| class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
|| class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
return AMD64_MEMORY;
return AMD64_SSE;
}
static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
static int
amd64_non_pod_p (struct type *type)
{
if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
return 1;
return 0;
}
static void
amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
{
int len = TYPE_LENGTH (type);
if (len > 16 || amd64_non_pod_p (type))
{
class[0] = class[1] = AMD64_MEMORY;
return;
}
class[0] = class[1] = AMD64_NO_CLASS;
if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
{
struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
amd64_classify (subtype, class);
if (len > 8 && class[1] == AMD64_NO_CLASS)
class[1] = class[0];
}
else
{
int i;
gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
|| TYPE_CODE (type) == TYPE_CODE_UNION);
for (i = 0; i < TYPE_NFIELDS (type); i++)
{
struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
int pos = TYPE_FIELD_BITPOS (type, i) / 64;
enum amd64_reg_class subclass[2];
if (TYPE_FIELD_STATIC (type, i))
continue;
gdb_assert (pos == 0 || pos == 1);
amd64_classify (subtype, subclass);
class[pos] = amd64_merge_classes (class[pos], subclass[0]);
if (pos == 0)
class[1] = amd64_merge_classes (class[1], subclass[1]);
}
}
if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
class[0] = class[1] = AMD64_MEMORY;
if (class[0] == AMD64_SSEUP)
class[0] = AMD64_SSE;
if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
class[1] = AMD64_SSE;
}
static void
amd64_classify (struct type *type, enum amd64_reg_class class[2])
{
enum type_code code = TYPE_CODE (type);
int len = TYPE_LENGTH (type);
class[0] = class[1] = AMD64_NO_CLASS;
if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
|| code == TYPE_CODE_RANGE || code == TYPE_CODE_BOOL
|| code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
&& (len == 1 || len == 2 || len == 4 || len == 8))
class[0] = AMD64_INTEGER;
else if (code == TYPE_CODE_FLT && (len == 4 || len == 8))
class[0] = AMD64_SSE;
else if (code == TYPE_CODE_FLT && len == 16)
class[0] = AMD64_X87, class[1] = AMD64_X87UP;
else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
|| code == TYPE_CODE_UNION)
amd64_classify_aggregate (type, class);
}
static enum return_value_convention
amd64_return_value (struct gdbarch *gdbarch, struct type *type,
struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
enum amd64_reg_class class[2];
int len = TYPE_LENGTH (type);
static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM };
static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM };
int integer_reg = 0;
int sse_reg = 0;
int i;
gdb_assert (!(readbuf && writebuf));
amd64_classify (type, class);
if (class[0] == AMD64_MEMORY)
{
if (readbuf)
{
ULONGEST addr;
regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr);
read_memory (addr, readbuf, TYPE_LENGTH (type));
}
return RETURN_VALUE_ABI_RETURNS_ADDRESS;
}
gdb_assert (class[1] != AMD64_MEMORY);
gdb_assert (len <= 16);
for (i = 0; len > 0; i++, len -= 8)
{
int regnum = -1;
int offset = 0;
switch (class[i])
{
case AMD64_INTEGER:
regnum = integer_regnum[integer_reg++];
break;
case AMD64_SSE:
regnum = sse_regnum[sse_reg++];
break;
case AMD64_SSEUP:
gdb_assert (sse_reg > 0);
regnum = sse_regnum[sse_reg - 1];
offset = 8;
break;
case AMD64_X87:
regnum = AMD64_ST0_REGNUM;
if (writebuf)
i387_return_value (gdbarch, regcache);
break;
case AMD64_X87UP:
gdb_assert (i > 0 && class[0] == AMD64_X87);
regnum = AMD64_ST0_REGNUM;
offset = 8;
len = 2;
break;
case AMD64_NO_CLASS:
continue;
default:
gdb_assert (!"Unexpected register class.");
}
gdb_assert (regnum != -1);
if ((readbuf || writebuf)
&& (regnum == sse_regnum[0] || regnum == sse_regnum[1]))
{
if (readbuf)
swapped_regcache_raw_read_part (regcache, regnum, offset,
min (len, 8), readbuf + i * 8);
if (writebuf)
swapped_regcache_raw_write_part (regcache, regnum, offset,
min (len, 8), writebuf + i * 8);
continue;
}
if (readbuf)
regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
readbuf + i * 8);
if (writebuf)
regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
writebuf + i * 8);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
static CORE_ADDR
amd64_push_arguments (struct regcache *regcache, int nargs,
struct value **args, CORE_ADDR sp, int struct_return)
{
static int integer_regnum[] =
{
AMD64_RDI_REGNUM,
AMD64_RSI_REGNUM,
AMD64_RDX_REGNUM,
AMD64_RCX_REGNUM,
8,
9
};
static int sse_regnum[] =
{
AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM,
AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3,
AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5,
AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7,
};
struct value **stack_args = alloca (nargs * sizeof (struct value *));
int num_stack_args = 0;
int num_elements = 0;
int element = 0;
int integer_reg = 0;
int sse_reg = 0;
int i;
if (struct_return)
integer_reg++;
for (i = 0; i < nargs; i++)
{
struct type *type = value_type (args[i]);
int len = TYPE_LENGTH (type);
enum amd64_reg_class class[2];
int needed_integer_regs = 0;
int needed_sse_regs = 0;
int j;
amd64_classify (type, class);
for (j = 0; j < 2; j++)
{
if (class[j] == AMD64_INTEGER)
needed_integer_regs++;
else if (class[j] == AMD64_SSE)
needed_sse_regs++;
}
if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
|| sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
|| (needed_integer_regs == 0 && needed_sse_regs == 0))
{
num_elements += ((len + 7) / 8);
stack_args[num_stack_args++] = args[i];
}
else
{
const gdb_byte *valbuf = value_contents (args[i]);
gdb_byte buf[8];
gdb_assert (len <= 16);
for (j = 0; len > 0; j++, len -= 8)
{
int regnum = -1;
int offset = 0;
switch (class[j])
{
case AMD64_INTEGER:
regnum = integer_regnum[integer_reg++];
break;
case AMD64_SSE:
regnum = sse_regnum[sse_reg++];
break;
case AMD64_SSEUP:
gdb_assert (sse_reg > 0);
regnum = sse_regnum[sse_reg - 1];
offset = 8;
break;
default:
gdb_assert (!"Unexpected register class.");
}
gdb_assert (regnum != -1);
memset (buf, 0, sizeof buf);
memcpy (buf, valbuf + j * 8, min (len, 8));
if (class[j] == AMD64_SSE || class[j] == AMD64_SSEUP)
swapped_regcache_raw_write_part (regcache, regnum, offset, 8,
buf);
else
regcache_raw_write_part (regcache, regnum, offset, 8, buf);
}
}
}
sp -= num_elements * 8;
sp &= ~0xf;
for (i = 0; i < num_stack_args; i++)
{
struct type *type = value_type (stack_args[i]);
const gdb_byte *valbuf = value_contents (stack_args[i]);
int len = TYPE_LENGTH (type);
write_memory (sp + element * 8, valbuf, len);
element += ((len + 7) / 8);
}
regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg);
return sp;
}
static CORE_ADDR
amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
int struct_return, CORE_ADDR struct_addr)
{
gdb_byte buf[8];
sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
if (struct_return)
{
store_unsigned_integer (buf, 8, struct_addr);
regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf);
}
sp -= 8;
store_unsigned_integer (buf, 8, bp_addr);
write_memory (sp, buf, 8);
store_unsigned_integer (buf, 8, sp);
regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf);
regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf);
return sp + 16;
}
#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
static CORE_ADDR
amd64_skip_prologue (CORE_ADDR start_pc)
{
struct x86_frame_cache cache;
CORE_ADDR pc, endaddr;
x86_initialize_frame_cache (&cache, 8);
if (find_pc_partial_function_no_inlined (start_pc, NULL, NULL, &endaddr) == 0)
endaddr = start_pc + 512;
endaddr = refine_prologue_limit (start_pc, endaddr, 3);
pc = x86_analyze_prologue (start_pc, endaddr, &cache);
return pc;
}
static const struct frame_unwind amd64_frame_unwind =
{
NORMAL_FRAME,
x86_frame_this_id,
x86_frame_prev_register,
NULL,
NULL,
NULL
};
static const struct frame_unwind *
amd64_frame_sniffer (struct frame_info *next_frame)
{
return &amd64_frame_unwind;
}
static struct x86_frame_cache *
amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
{
struct x86_frame_cache *cache;
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
CORE_ADDR addr;
gdb_byte buf[8];
int i;
if (*this_cache)
return *this_cache;
cache = x86_alloc_frame_cache (8);
frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf);
cache->frame_base = extract_unsigned_integer (buf, 8);
addr = tdep->sigcontext_addr (next_frame);
gdb_assert (tdep->sc_reg_offset);
gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
for (i = 0; i < tdep->sc_num_regs; i++)
if (tdep->sc_reg_offset[i] != -1)
cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
cache->saved_regs_are_absolute = 1;
cache->prologue_scan_status = full_scan_succeeded;
cache->saved_regs_are_absolute = 1;
*this_cache = cache;
return cache;
}
static void
amd64_sigtramp_frame_this_id (struct frame_info *next_frame,
void **this_cache, struct frame_id *this_id)
{
struct x86_frame_cache *cache =
amd64_sigtramp_frame_cache (next_frame, this_cache);
(*this_id) = frame_id_build (cache->frame_base + 8, frame_pc_unwind (next_frame));
}
static void
amd64_sigtramp_frame_prev_register (struct frame_info *next_frame,
void **this_cache,
int regnum, enum opt_state *optimizedp,
enum lval_type *lvalp, CORE_ADDR *addrp,
int *realnump, gdb_byte *valuep)
{
amd64_sigtramp_frame_cache (next_frame, this_cache);
x86_frame_prev_register (next_frame, this_cache, regnum,
optimizedp, lvalp, addrp, realnump, valuep);
}
static const struct frame_unwind amd64_sigtramp_frame_unwind =
{
SIGTRAMP_FRAME,
amd64_sigtramp_frame_this_id,
amd64_sigtramp_frame_prev_register,
NULL,
NULL,
NULL
};
static const struct frame_unwind *
amd64_sigtramp_frame_sniffer (struct frame_info *next_frame)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
if (tdep->sigcontext_addr == NULL)
return NULL;
if (tdep->sigtramp_p != NULL)
{
if (tdep->sigtramp_p (next_frame))
return &amd64_sigtramp_frame_unwind;
}
if (tdep->sigtramp_start != 0)
{
CORE_ADDR pc = frame_pc_unwind (next_frame);
gdb_assert (tdep->sigtramp_end != 0);
if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
return &amd64_sigtramp_frame_unwind;
}
return NULL;
}
static CORE_ADDR
amd64_frame_base_address (struct frame_info *next_frame, void **this_cache)
{
struct x86_frame_cache *cache = x86_frame_cache (next_frame, this_cache, 8);
return cache->frame_base;
}
static const struct frame_base amd64_frame_base =
{
&amd64_frame_unwind,
amd64_frame_base_address,
amd64_frame_base_address,
amd64_frame_base_address
};
static struct frame_id
amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
gdb_byte buf[8];
CORE_ADDR fp;
frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf);
fp = extract_unsigned_integer (buf, 8);
return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
}
static CORE_ADDR
amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
{
return sp & -(CORE_ADDR)16;
}
static void
amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
int regnum, const void *fpregs, size_t len)
{
const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
gdb_assert (len == tdep->sizeof_fpregset);
amd64_supply_fxsave (regcache, regnum, fpregs);
}
static void
amd64_collect_fpregset (const struct regset *regset,
const struct regcache *regcache,
int regnum, void *fpregs, size_t len)
{
const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch);
gdb_assert (len == tdep->sizeof_fpregset);
amd64_collect_fxsave (regcache, regnum, fpregs);
}
static CORE_ADDR
amd64_fetch_pointer_argument (struct frame_info *frame, int argi,
struct type *type)
{
static int integer_regnum[] =
{
AMD64_RDI_REGNUM,
AMD64_RSI_REGNUM,
AMD64_RDX_REGNUM,
AMD64_RCX_REGNUM,
8,
9
};
if (argi < 6)
return get_frame_register_unsigned (frame, integer_regnum[argi]);
else
return 0;
}
static const struct regset *
amd64_regset_from_core_section (struct gdbarch *gdbarch,
const char *sect_name, size_t sect_size)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
{
if (tdep->fpregset == NULL)
tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset,
amd64_collect_fpregset);
return tdep->fpregset;
}
return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
}
void
amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
tdep->st0_regnum = AMD64_ST0_REGNUM;
tdep->num_xmm_regs = 16;
set_gdbarch_long_bit (gdbarch, 64);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_ptr_bit (gdbarch, 64);
set_gdbarch_long_double_bit (gdbarch, 128);
set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
set_gdbarch_register_name (gdbarch, amd64_register_name);
set_gdbarch_register_type (gdbarch, amd64_register_type);
set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM);
set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM);
set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM);
set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM);
set_gdbarch_deprecated_fp_regnum (gdbarch, AMD64_RBP_REGNUM);
set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
set_gdbarch_frame_align (gdbarch, amd64_frame_align);
set_gdbarch_frame_red_zone_size (gdbarch, 128);
set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p);
set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
set_gdbarch_return_value (gdbarch, amd64_return_value);
set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
set_gdbarch_num_pseudo_regs (gdbarch, 0);
tdep->mm0_regnum = -1;
set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
frame_base_set_default (gdbarch, &amd64_frame_base);
if (tdep->gregset_reg_offset)
set_gdbarch_regset_from_core_section (gdbarch,
amd64_regset_from_core_section);
set_gdbarch_fetch_pointer_argument (gdbarch, amd64_fetch_pointer_argument);
}
#define I387_ST0_REGNUM AMD64_ST0_REGNUM
void
amd64_supply_fxsave (struct regcache *regcache, int regnum,
const void *fxsave)
{
i387_supply_fxsave (regcache, regnum, fxsave);
if (fxsave && gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
{
const gdb_byte *regs = fxsave;
if (regnum == -1 || regnum == I387_FISEG_REGNUM)
regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12);
if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20);
}
}
void
amd64_collect_fxsave (const struct regcache *regcache, int regnum,
void *fxsave)
{
gdb_byte *regs = fxsave;
i387_collect_fxsave (regcache, regnum, fxsave);
if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
{
if (regnum == -1 || regnum == I387_FISEG_REGNUM)
regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12);
if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20);
}
}