#define perform_udivsi3(arg0,arg1) \
{ \
register int dx asm("dx"); \
register int ax asm("ax"); \
\
dx = 0; \
ax = arg0; \
asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \
return ax; \
}
#define perform_divsi3(arg0,arg1) \
{ \
register int dx asm("dx"); \
register int ax asm("ax"); \
register int cx asm("cx"); \
\
ax = arg0; \
cx = arg1; \
asm ("cltd\n\tidivl %3" : "=a" (ax), "=&d" (dx) : "a" (ax), "c" (cx)); \
return ax; \
}
#define perform_umodsi3(arg0,arg1) \
{ \
register int dx asm("dx"); \
register int ax asm("ax"); \
\
dx = 0; \
ax = arg0; \
asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \
return dx; \
}
#define perform_modsi3(arg0,arg1) \
{ \
register int dx asm("dx"); \
register int ax asm("ax"); \
register int cx asm("cx"); \
\
ax = arg0; \
cx = arg1; \
asm ("cltd\n\tidivl %3" : "=a" (ax), "=&d" (dx) : "a" (ax), "c" (cx)); \
return dx; \
}
#define perform_fixdfsi(arg0) \
{ \
auto unsigned short ostatus; \
auto unsigned short nstatus; \
auto int ret; \
auto double tmp; \
\
&ostatus; \
&nstatus; \
&ret; \
&tmp; \
\
asm volatile ("fnstcw %0" : "=m" (ostatus)); \
nstatus = ostatus | 0x0c00; \
asm volatile ("fldcw %0" : : "m" (nstatus)); \
tmp = arg0; \
asm volatile ("fldl %0" : : "m" (tmp)); \
asm volatile ("fistpl %0" : "=m" (ret)); \
asm volatile ("fldcw %0" : : "m" (ostatus)); \
\
return ret; \
}