2007-12-05 James Grosbach Backport from mainline: 2007-07-05 Richard Earnshaw * arm.c (vfp3_const_double_index): Copy signed results of REAL_VALUE_TO_INT into unsigned vars. 2007-07-03 Julian Brown * config.gcc (with_fpu): Allow --with-fpu=vfp3. * config/arm/aout.h (REGISTER_NAMES): Add D16-D31. * config/arm/aof.h (REGISTER_NAMES): Add D16-D31. * config/arm/arm.c (FL_VFPV3): New flag for VFPv3 processor capability. (all_fpus): Add FPUTYPE_VFP3. (fp_model_for_fpu): Add VFPv3 field. (arm_rtx_costs_1): Give cost to VFPv3 constants. (vfp3_const_double_index): New function. Return integer index of VFPv3 constant suitable for fconst[sd] insns, or -1 if constant isn't suitable. (vfp3_const_double_rtx): New function. True if VFPv3 is enabled and argument represents a valid RTX for a VFPv3 constant. (vfp_output_fldmd): Split fldmd with > 16 registers in the list into two instructions. (vfp_emit_fstmd): Similar, for fstmd. (arm_print_operand): Implement new code 'G' for VFPv3 floating-point constants, represented as integer indices. (arm_hard_regno_mode_ok): Use VFP_REGNO_OK_FOR_SINGLE, VFP_REGNO_OK_FOR_DOUBLE macros. (arm_regno_class): Handle VFPv3 d0-d7, low, high register split. (arm_file_start): Set float-abi attribute for VFPv3, and output correct ".fpu" assembler directive. (arm_dbx_register_numbering): Add FIXME. * config/arm/arm.h (TARGET_VFP3): New macro. Target supports VFPv3. (fputype): Add FPUTYPE_VFP3. (FIXED_REGISTERS): Add 32 registers for D16-D31. (CALL_USED_REGISTERS): Likewise. (CONDITIONAL_REGISTER_USAGE): Add note about conditional definition of LAST_VFP_REGNUM. Make D16-D31 caller-saved, if present. (LAST_VFP_REGNUM): Extend available VFP registers for VFPv3. (D7_VFP_REGNUM): New. (LAST_LO_VFP_REGNUM, FIRST_HI_VFP_REGNUM, LAST_HI_VFP_REGNUM) (VFP_REGNO_OK_FOR_SINGLE, VFP_REGNO_OK_FOR_SINGLE) (VFP_REGNO_OK_FOR_DOUBLE): Define new macros. (FIRST_PSEUDO_REGISTER): Shift up to 128 to accommodate VFPv3. (REG_ALLOC_ORDER): Adjust for VFPv3. (reg_class): Add VFP_D0_D7_REGS, VFP_LO_REGS, VFP_HI_REGS. (REG_CLASS_NAMES): Add entries corresponding to VFP_D0_D7_REGS, VFP_LO_REGS, VFP_HI_REGS. (REG_CLASS_CONTENTS): Likewise. Extend contents for VFP_REGS. (IS_VFP_CLASS): Define macro. (SECONDARY_OUTPUT_RELOAD_CLASS, SECONDARY_INPUT_RELOAD_CLASS): Use IS_VFP_CLASS. (REGISTER_MOVE_COST): Likewise. * config/arm/arm-protos.h (vfp3_const_double_rtx): Add prototype. * config/arm/vfp.md (VFPCC_REGNUM): Redefine as 127. (*arm_movsi_vfp, *thumb2_movsi_vfp, *movsfcc_vfp) 2007-02-21 Paul Brook * config/arm/arm.c (thumb2_final_prescan_insn): Don't incrememnt condexec_count when skipping USE and CLOBBER. 2007-01-10 Paul Brook * config/arm/arm.c (arm_rtx_costs_1): Handle mutiply-subtract. * config/arm/arm.md (mulsi3subsi): New insn. 2007-01-09 Nicolas Pitre PR target/30173 * arm/ieee754-df.S (Lad_s): Also test the low word of X for zero. 2007-01-04 Paul Brook * config/arm/arm.md (arm_mulsi3, thumb_mulsi3, mulsi3_compare0, mulsi_compare0_scratch, mulsi3addsi, mulsi3addsi_compare0, mulsi3addsi_compare0_scratch, mulsidi3adddi, mulsidi3, umulsidi3, umulsidi3adddi, smulsi3_highpart, umulsi3_highpart): Make conditional on !arm_arch6. (arm_mulsi3_v6, thumb_mulsi3_v6, mulsi3_compare0_v6, mulsi_compare0_scratch_v6, mulsi3addsi_v6, mulsi3addsi_compare0_v6, mulsi3addsi_compare0_scratch_v6, mulsidi3adddi_v6, mulsidi3_v6, umulsidi3_v6, umulsidi3adddi_v6, smulsi3_highpart_v6, umulsi3_highpart_v6): New insns.