extern char *asm_file_name;
extern char call_used_regs[];
extern int may_call_alloca;
extern char **save_argv;
extern int target_flags;
enum cmp_type {
CMP_SI,
CMP_DI,
CMP_SF,
CMP_DF,
CMP_MAX
};
enum delay_type {
DELAY_NONE,
DELAY_LOAD,
DELAY_HILO,
DELAY_FCMP
};
enum processor_type {
PROCESSOR_DEFAULT,
PROCESSOR_R3000,
PROCESSOR_R3900,
PROCESSOR_R6000,
PROCESSOR_R4000,
PROCESSOR_R4100,
PROCESSOR_R4111,
PROCESSOR_R4120,
PROCESSOR_R4300,
PROCESSOR_R4600,
PROCESSOR_R4650,
PROCESSOR_R5000,
PROCESSOR_R5400,
PROCESSOR_R5500,
PROCESSOR_R8000,
PROCESSOR_R4KC,
PROCESSOR_R5KC,
PROCESSOR_R20KC,
PROCESSOR_SR71000,
PROCESSOR_SB1
};
#define mips_cpu_attr ((enum attr_cpu)mips_tune)
#define ABI_32 0
#define ABI_N32 1
#define ABI_64 2
#define ABI_EABI 3
#define ABI_O64 4
#define ABI_MEABI 5
enum mips_abicalls_type {
MIPS_ABICALLS_NO,
MIPS_ABICALLS_YES
};
#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
enum block_move_type {
BLOCK_MOVE_NORMAL,
BLOCK_MOVE_NOT_LAST,
BLOCK_MOVE_LAST
};
struct mips_cpu_info {
const char *name;
enum processor_type cpu;
int isa;
};
extern char mips_reg_names[][8];
extern char mips_print_operand_punct[256];
extern const char *current_function_file;
extern int num_source_filenames;
extern int inside_function;
extern int ignore_line_number;
extern int file_in_function_warning;
extern int sdb_label_count;
extern int sdb_begin_function_line;
extern int mips_section_threshold;
extern int g_switch_value;
extern int g_switch_set;
extern int sym_lineno;
extern int set_noreorder;
extern int set_nomacro;
extern int set_noat;
extern int set_volatile;
extern int mips_branch_likely;
extern int mips_dbx_regno[];
extern GTY(()) rtx branch_cmp[2];
extern enum cmp_type branch_type;
extern enum processor_type mips_arch;
extern enum processor_type mips_tune;
extern enum mips_abicalls_type mips_abicalls;
extern int mips_isa;
extern int mips16;
extern int mips16_hard_float;
extern int mips_entry;
extern const char *mips_arch_string;
extern const char *mips_tune_string;
extern const char *mips_isa_string;
extern const char *mips_abi_string;
extern const char *mips_entry_string;
extern const char *mips_no_mips16_string;
extern const char *mips_cache_flush_func;
extern int mips_split_addresses;
extern int dslots_load_total;
extern int dslots_load_filled;
extern int dslots_jump_total;
extern int dslots_jump_filled;
extern int dslots_number_nops;
extern int num_refs[3];
extern GTY(()) rtx mips_load_reg;
extern GTY(()) rtx mips_load_reg2;
extern GTY(()) rtx mips_load_reg3;
extern GTY(()) rtx mips_load_reg4;
extern int mips_string_length;
extern const struct mips_cpu_info mips_cpu_info_table[];
extern const struct mips_cpu_info *mips_arch_info;
extern const struct mips_cpu_info *mips_tune_info;
extern void sdata_section PARAMS ((void));
extern void sbss_section PARAMS ((void));
#define BITMASK_HIGH (((unsigned long)1) << 31)
#define BITMASK_UPPER16 ((unsigned long)0xffff << 16)
#define BITMASK_LOWER16 ((unsigned long)0xffff)
#define MASK_INT64 0x00000001
#define MASK_LONG64 0x00000002
#define MASK_SPLIT_ADDR 0x00000004
#define MASK_GPOPT 0x00000008
#define MASK_GAS 0x00000010
#define MASK_NAME_REGS 0x00000020
#define MASK_STATS 0x00000040
#define MASK_MEMCPY 0x00000080
#define MASK_SOFT_FLOAT 0x00000100
#define MASK_FLOAT64 0x00000200
#define MASK_ABICALLS 0x00000400
#define MASK_UNUSED1 0x00000800
#define MASK_LONG_CALLS 0x00001000
#define MASK_64BIT 0x00002000
#define MASK_EMBEDDED_PIC 0x00004000
#define MASK_EMBEDDED_DATA 0x00008000
#define MASK_BIG_ENDIAN 0x00010000
#define MASK_SINGLE_FLOAT 0x00020000
#define MASK_MAD 0x00040000
#define MASK_4300_MUL_FIX 0x00080000
#define MASK_MIPS16 0x00100000
#define MASK_NO_CHECK_ZERO_DIV \
0x00200000
#define MASK_CHECK_RANGE_DIV \
0x00400000
#define MASK_UNINIT_CONST_IN_RODATA \
0x00800000
#define MASK_NO_FUSED_MADD 0x01000000
#define MASK_BRANCHLIKELY 0x02000000
#define MASK_DEBUG 0
#define MASK_DEBUG_A 0
#define MASK_DEBUG_B 0
#define MASK_DEBUG_C 0
#define MASK_DEBUG_D 0
#define MASK_DEBUG_E 0
#define MASK_DEBUG_F 0
#define MASK_DEBUG_G 0
#define MASK_DEBUG_I 0
#define MASK_MIPS_TFILE 0
#define TARGET_INT64 (target_flags & MASK_INT64)
#define TARGET_LONG64 (target_flags & MASK_LONG64)
#define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
#define TARGET_64BIT (target_flags & MASK_64BIT)
#define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
#define TARGET_GAS (target_flags & MASK_GAS)
#define TARGET_MIPS_AS (!TARGET_GAS)
#define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
#define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
#define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
#define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
#define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
#define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
#define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
#define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
#define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
#define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
#define TARGET_GP_OPT (target_flags & MASK_GPOPT)
#define TARGET_STATS (target_flags & MASK_STATS)
#define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
#define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
#define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
#define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
#define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
#define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
#define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
#define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
#define TARGET_MAD (target_flags & MASK_MAD)
#define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
#define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
#define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
#define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
#define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
#define TARGET_FILE_SWITCHING \
(TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
#define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
#define ISA_MIPS1 (mips_isa == 1)
#define ISA_MIPS2 (mips_isa == 2)
#define ISA_MIPS3 (mips_isa == 3)
#define ISA_MIPS4 (mips_isa == 4)
#define ISA_MIPS32 (mips_isa == 32)
#define ISA_MIPS64 (mips_isa == 64)
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
#define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
#define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
#define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
#define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
#define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
#define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
#define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
#define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
#define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
#define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
do \
{ \
char *macro, *p; \
\
macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
for (p = macro; *p != 0; p++) \
*p = TOUPPER (*p); \
\
builtin_define (macro); \
builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
free (macro); \
} \
while (0)
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_assert ("cpu=mips"); \
builtin_define ("__mips__"); \
builtin_define ("_mips"); \
\
\
if (!flag_iso) \
builtin_define ("mips"); \
\
\
if (TARGET_64BIT) \
{ \
builtin_define ("__mips64"); \
builtin_define_std ("R4000"); \
builtin_define ("_R4000"); \
} \
else \
{ \
builtin_define_std ("R3000"); \
builtin_define ("_R3000"); \
} \
if (TARGET_FLOAT64) \
builtin_define ("__mips_fpr=64"); \
else \
builtin_define ("__mips_fpr=32"); \
\
if (TARGET_MIPS16) \
builtin_define ("__mips16"); \
\
MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
\
if (ISA_MIPS1) \
{ \
builtin_define ("__mips=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
} \
else if (ISA_MIPS2) \
{ \
builtin_define ("__mips=2"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
} \
else if (ISA_MIPS3) \
{ \
builtin_define ("__mips=3"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
} \
else if (ISA_MIPS4) \
{ \
builtin_define ("__mips=4"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
} \
else if (ISA_MIPS32) \
{ \
builtin_define ("__mips=32"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
} \
else if (ISA_MIPS64) \
{ \
builtin_define ("__mips=64"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
} \
\
if (TARGET_HARD_FLOAT) \
builtin_define ("__mips_hard_float"); \
else if (TARGET_SOFT_FLOAT) \
builtin_define ("__mips_soft_float"); \
\
if (TARGET_SINGLE_FLOAT) \
builtin_define ("__mips_single_float"); \
\
if (TARGET_BIG_ENDIAN) \
{ \
builtin_define_std ("MIPSEB"); \
builtin_define ("_MIPSEB"); \
} \
else \
{ \
builtin_define_std ("MIPSEL"); \
builtin_define ("_MIPSEL"); \
} \
\
\
if (preprocessing_asm_p ()) \
{ \
builtin_define_std ("LANGUAGE_ASSEMBLY"); \
builtin_define ("_LANGUAGE_ASSEMBLY"); \
} \
else if (c_language == clk_c) \
{ \
builtin_define_std ("LANGUAGE_C"); \
builtin_define ("_LANGUAGE_C"); \
} \
else if (c_language == clk_cplusplus) \
{ \
builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
} \
if (flag_objc) \
{ \
builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
\
builtin_define_std ("LANGUAGE_C"); \
builtin_define ("_LANGUAGE_C"); \
} \
\
if (mips_abi == ABI_EABI) \
builtin_define ("__mips_eabi"); \
\
} while (0)
#define TARGET_SWITCHES \
{ \
{"no-crt0", 0, \
N_("No default crt0.o") }, \
{"int64", MASK_INT64 | MASK_LONG64, \
N_("Use 64-bit int type")}, \
{"long64", MASK_LONG64, \
N_("Use 64-bit long type")}, \
{"long32", -(MASK_LONG64 | MASK_INT64), \
N_("Use 32-bit long type")}, \
{"split-addresses", MASK_SPLIT_ADDR, \
N_("Optimize lui/addiu address loads")}, \
{"no-split-addresses", -MASK_SPLIT_ADDR, \
N_("Don't optimize lui/addiu address loads")}, \
{"mips-as", -MASK_GAS, \
N_("Use MIPS as")}, \
{"gas", MASK_GAS, \
N_("Use GNU as")}, \
{"rnames", MASK_NAME_REGS, \
N_("Use symbolic register names")}, \
{"no-rnames", -MASK_NAME_REGS, \
N_("Don't use symbolic register names")}, \
{"gpOPT", MASK_GPOPT, \
N_("Use GP relative sdata/sbss sections")}, \
{"gpopt", MASK_GPOPT, \
N_("Use GP relative sdata/sbss sections")}, \
{"no-gpOPT", -MASK_GPOPT, \
N_("Don't use GP relative sdata/sbss sections")}, \
{"no-gpopt", -MASK_GPOPT, \
N_("Don't use GP relative sdata/sbss sections")}, \
{"stats", MASK_STATS, \
N_("Output compiler statistics")}, \
{"no-stats", -MASK_STATS, \
N_("Don't output compiler statistics")}, \
{"memcpy", MASK_MEMCPY, \
N_("Don't optimize block moves")}, \
{"no-memcpy", -MASK_MEMCPY, \
N_("Optimize block moves")}, \
{"mips-tfile", MASK_MIPS_TFILE, \
N_("Use mips-tfile asm postpass")}, \
{"no-mips-tfile", -MASK_MIPS_TFILE, \
N_("Don't use mips-tfile asm postpass")}, \
{"soft-float", MASK_SOFT_FLOAT, \
N_("Use software floating point")}, \
{"hard-float", -MASK_SOFT_FLOAT, \
N_("Use hardware floating point")}, \
{"fp64", MASK_FLOAT64, \
N_("Use 64-bit FP registers")}, \
{"fp32", -MASK_FLOAT64, \
N_("Use 32-bit FP registers")}, \
{"gp64", MASK_64BIT, \
N_("Use 64-bit general registers")}, \
{"gp32", -MASK_64BIT, \
N_("Use 32-bit general registers")}, \
{"abicalls", MASK_ABICALLS, \
N_("Use Irix PIC")}, \
{"no-abicalls", -MASK_ABICALLS, \
N_("Don't use Irix PIC")}, \
{"long-calls", MASK_LONG_CALLS, \
N_("Use indirect calls")}, \
{"no-long-calls", -MASK_LONG_CALLS, \
N_("Don't use indirect calls")}, \
{"embedded-pic", MASK_EMBEDDED_PIC, \
N_("Use embedded PIC")}, \
{"no-embedded-pic", -MASK_EMBEDDED_PIC, \
N_("Don't use embedded PIC")}, \
{"embedded-data", MASK_EMBEDDED_DATA, \
N_("Use ROM instead of RAM")}, \
{"no-embedded-data", -MASK_EMBEDDED_DATA, \
N_("Don't use ROM instead of RAM")}, \
{"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
{"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
N_("Don't put uninitialized constants in ROM")}, \
{"eb", MASK_BIG_ENDIAN, \
N_("Use big-endian byte order")}, \
{"el", -MASK_BIG_ENDIAN, \
N_("Use little-endian byte order")}, \
{"single-float", MASK_SINGLE_FLOAT, \
N_("Use single (32-bit) FP only")}, \
{"double-float", -MASK_SINGLE_FLOAT, \
N_("Don't use single (32-bit) FP only")}, \
{"mad", MASK_MAD, \
N_("Use multiply accumulate")}, \
{"no-mad", -MASK_MAD, \
N_("Don't use multiply accumulate")}, \
{"no-fused-madd", MASK_NO_FUSED_MADD, \
N_("Don't generate fused multiply/add instructions")}, \
{"fused-madd", -MASK_NO_FUSED_MADD, \
N_("Generate fused multiply/add instructions")}, \
{"fix4300", MASK_4300_MUL_FIX, \
N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
N_("Don't work around early 4300 hardware bug")}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
N_("Trap on integer divide by zero")}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
N_("Don't trap on integer divide by zero")}, \
{"check-range-division",MASK_CHECK_RANGE_DIV, \
N_("Trap on integer divide overflow")}, \
{"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
N_("Don't trap on integer divide overflow")}, \
{ "branch-likely", MASK_BRANCHLIKELY, \
N_("Use Branch Likely instructions, overriding default for arch")}, \
{ "no-branch-likely", -MASK_BRANCHLIKELY, \
N_("Don't use Branch Likely instructions, overriding default for arch")}, \
{"debug", MASK_DEBUG, \
NULL}, \
{"debuga", MASK_DEBUG_A, \
NULL}, \
{"debugb", MASK_DEBUG_B, \
NULL}, \
{"debugc", MASK_DEBUG_C, \
NULL}, \
{"debugd", MASK_DEBUG_D, \
NULL}, \
{"debuge", MASK_DEBUG_E, \
NULL}, \
{"debugf", MASK_DEBUG_F, \
NULL}, \
{"debugg", MASK_DEBUG_G, \
NULL}, \
{"debugi", MASK_DEBUG_I, \
NULL}, \
{"", (TARGET_DEFAULT \
| TARGET_CPU_DEFAULT \
| TARGET_ENDIAN_DEFAULT), \
NULL}, \
}
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#endif
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#endif
#ifndef TARGET_ENDIAN_DEFAULT
#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
#endif
#ifndef MIPS_ISA_DEFAULT
#ifndef MIPS_CPU_STRING_DEFAULT
#define MIPS_CPU_STRING_DEFAULT "from-abi"
#endif
#endif
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
#ifdef __mips64
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#endif
#ifndef MULTILIB_ENDIAN_DEFAULT
#if TARGET_ENDIAN_DEFAULT == 0
#define MULTILIB_ENDIAN_DEFAULT "EL"
#else
#define MULTILIB_ENDIAN_DEFAULT "EB"
#endif
#endif
#ifndef MULTILIB_ISA_DEFAULT
# if MIPS_ISA_DEFAULT == 1
# define MULTILIB_ISA_DEFAULT "mips1"
# else
# if MIPS_ISA_DEFAULT == 2
# define MULTILIB_ISA_DEFAULT "mips2"
# else
# if MIPS_ISA_DEFAULT == 3
# define MULTILIB_ISA_DEFAULT "mips3"
# else
# if MIPS_ISA_DEFAULT == 4
# define MULTILIB_ISA_DEFAULT "mips4"
# else
# if MIPS_ISA_DEFAULT == 32
# define MULTILIB_ISA_DEFAULT "mips32"
# else
# if MIPS_ISA_DEFAULT == 64
# define MULTILIB_ISA_DEFAULT "mips64"
# else
# define MULTILIB_ISA_DEFAULT "mips1"
# endif
# endif
# endif
# endif
# endif
# endif
#endif
#ifndef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS \
{ MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
#endif
#ifndef ENDIAN_SPEC
#if TARGET_ENDIAN_DEFAULT == 0
#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
#else
#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
#endif
#endif
#define TARGET_OPTIONS \
{ \
SUBTARGET_TARGET_OPTIONS \
{ "tune=", &mips_tune_string, \
N_("Specify CPU for scheduling purposes")}, \
{ "arch=", &mips_arch_string, \
N_("Specify CPU for code generation purposes")}, \
{ "abi=", &mips_abi_string, \
N_("Specify an ABI")}, \
{ "ips", &mips_isa_string, \
N_("Specify a Standard MIPS ISA")}, \
{ "entry", &mips_entry_string, \
N_("Use mips16 entry/exit psuedo ops")}, \
{ "no-mips16", &mips_no_mips16_string, \
N_("Don't use MIPS16 instructions")}, \
{ "no-flush-func", &mips_cache_flush_func, \
N_("Don't call any cache flush functions")}, \
{ "flush-func=", &mips_cache_flush_func, \
N_("Specify cache flush function")}, \
}
#define SUBTARGET_TARGET_OPTIONS
#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
&& !TARGET_SR71K \
&& !TARGET_MIPS16)
#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| ISA_MIPS32 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
#define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
&& !TARGET_MIPS16)
#define HAVE_SQRT_P() (!ISA_MIPS1)
#define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
|| mips_abi == ABI_O64 \
|| mips_abi == ABI_N32)
#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|| ISA_MIPS4 \
|| ISA_MIPS64)
#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
&& !TARGET_MIPS5500)
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS64) \
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
#define ISA_HAS_INT_CONDMOVE 0
#define ISA_HAS_8CC (ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS64)
#define ISA_HAS_FP4 ((ISA_MIPS4 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
&& !TARGET_MIPS16)
#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
|| ISA_MIPS64 \
) && !TARGET_MIPS16)
#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
|| ISA_MIPS64) \
&& (!TARGET_MIPS5400 || TARGET_MAD) \
&& ! TARGET_MIPS16)
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS64 \
) && !TARGET_MIPS16)
#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
&& !TARGET_MIPS16)
#define ISA_HAS_MULHI (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_MULS (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_MSAC (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_MACC (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_ROTR_SI (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
#define ISA_HAS_ROTR_DI (TARGET_64BIT \
&& (TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
))
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS64) \
&& !TARGET_MIPS16)
#define ISA_HAS_TRUNC_W (!ISA_MIPS1)
#undef SWITCH_TAKES_ARG
#define SWITCH_TAKES_ARG(CHAR) \
(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
#define OVERRIDE_OPTIONS override_options ()
#define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
#define CAN_DEBUG_WITHOUT_FP
#ifndef NM_FLAGS
#define NM_FLAGS "-Bn"
#endif
#define MIPS_AS_ASM_SPEC "\
%{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
%{pipe: %e-pipe is not supported} \
%{K} %(subtarget_mips_as_asm_spec)"
#ifndef SUBTARGET_MIPS_AS_ASM_SPEC
#define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
#endif
#define GAS_ASM_SPEC "%{mtune=*} %{v}"
extern int mips_abi;
#ifndef MIPS_ABI_DEFAULT
#define MIPS_ABI_DEFAULT ABI_32
#endif
#if MIPS_ABI_DEFAULT == ABI_32
#define MULTILIB_ABI_DEFAULT "mabi=32"
#define ASM_ABI_DEFAULT_SPEC "-32"
#endif
#if MIPS_ABI_DEFAULT == ABI_O64
#define MULTILIB_ABI_DEFAULT "mabi=o64"
#define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
#endif
#if MIPS_ABI_DEFAULT == ABI_N32
#define MULTILIB_ABI_DEFAULT "mabi=n32"
#define ASM_ABI_DEFAULT_SPEC "-n32"
#endif
#if MIPS_ABI_DEFAULT == ABI_64
#define MULTILIB_ABI_DEFAULT "mabi=64"
#define ASM_ABI_DEFAULT_SPEC "-64"
#endif
#if MIPS_ABI_DEFAULT == ABI_EABI
#define MULTILIB_ABI_DEFAULT "mabi=eabi"
#define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
#endif
#if MIPS_ABI_DEFAULT == ABI_MEABI
#define MULTILIB_ABI_DEFAULT "mabi=meabi"
#define ASM_ABI_DEFAULT_SPEC ""
#endif
#ifndef OBJECT_FORMAT_ELF
#undef ASM_ABI_DEFAULT_SPEC
#define ASM_ABI_DEFAULT_SPEC ""
#endif
#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
#define TARGET_ASM_SPEC "\
%{mmips-as: %(mips_as_asm_spec)} \
%{!mmips-as: %(gas_asm_spec)}"
#else
#define TARGET_ASM_SPEC "\
%{!mgas: %(mips_as_asm_spec)} \
%{mgas: %(gas_asm_spec)}"
#endif
#ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
%{noasmopt:-O0} \
%{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
#endif
#ifndef SUBTARGET_ASM_DEBUGGING_SPEC
#define SUBTARGET_ASM_DEBUGGING_SPEC "\
%{g} %{g0} %{g1} %{g2} %{g3} \
%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
#endif
#ifndef SUBTARGET_ASM_SPEC
#define SUBTARGET_ASM_SPEC ""
#endif
#undef ASM_SPEC
#define ASM_SPEC "\
%{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
%{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
%(subtarget_asm_optimizing_spec) \
%(subtarget_asm_debugging_spec) \
%{membedded-pic} \
%{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
%{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
%{mgp32} %{mgp64} %{march=*} \
%(target_asm_spec) \
%(subtarget_asm_spec)"
#ifndef ASM_FINAL_SPEC
#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
#define ASM_FINAL_SPEC "\
%{mmips-as: %{!mno-mips-tfile: \
\n mips-tfile %{v*: -v} \
%{K: -I %b.o~} \
%{!K: %{save-temps: -I %b.o~}} \
%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
%{.s:%i} %{!.s:%g.s}}}"
#else
#define ASM_FINAL_SPEC "\
%{!mgas: %{!mno-mips-tfile: \
\n mips-tfile %{v*: -v} \
%{K: -I %b.o~} \
%{!K: %{save-temps: -I %b.o~}} \
%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
%{.s:%i} %{!.s:%g.s}}}"
#endif
#endif
#ifndef LIB_SPEC
#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
#endif
#ifndef LINK_SPEC
#define LINK_SPEC "\
%(endian_spec) \
%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
%{bestGnum} %{shared} %{non_shared}"
#endif
#ifndef SUBTARGET_CC1_SPEC
#define SUBTARGET_CC1_SPEC ""
#endif
#ifndef CC1_SPEC
#define CC1_SPEC "\
%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
%{save-temps: } \
%(subtarget_cc1_spec)"
#endif
#ifndef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC ""
#endif
#define CPP_SPEC "%(subtarget_cpp_spec)"
#define EXTRA_SPECS \
{ "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
{ "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
{ "gas_asm_spec", GAS_ASM_SPEC }, \
{ "target_asm_spec", TARGET_ASM_SPEC }, \
{ "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
{ "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
{ "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
{ "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
{ "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
{ "endian_spec", ENDIAN_SPEC }, \
SUBTARGET_EXTRA_SPECS
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
#ifndef MD_EXEC_PREFIX
#define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
#endif
#ifndef MD_STARTFILE_PREFIX
#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
#endif
#define MIPS_VERSION "[AL 1.1, MM 40]"
#ifndef MACHINE_TYPE
#define MACHINE_TYPE "BSD Mips"
#endif
#ifndef TARGET_VERSION_INTERNAL
#define TARGET_VERSION_INTERNAL(STREAM) \
fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
#endif
#ifndef TARGET_VERSION
#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
#endif
#define SDB_DEBUGGING_INFO 1
#define DBX_DEBUGGING_INFO 1
#define MIPS_DEBUGGING_INFO 1
#ifndef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
#endif
#define DEFAULT_GDB_EXTENSIONS 1
#define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
#define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
#define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
#ifndef LOCAL_LABEL_PREFIX
#define LOCAL_LABEL_PREFIX "$"
#endif
#ifndef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX ""
#endif
#define SDB_ALLOW_FORWARD_REFERENCES
#define SDB_ALLOW_UNKNOWN_REFERENCES
#undef DBX_CONTIN_LENGTH
#define DBX_CONTIN_LENGTH 1500
#define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
#define DWARF_FRAME_REGNUM(REG) \
(REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
#define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
#define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
#define DWARF_CIE_DATA_ALIGNMENT 4
#define PUT_SDB_SCL(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
} while (0)
#define PUT_SDB_INT_VAL(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t.val\t"); \
fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
fprintf (asm_out_text_file, ";"); \
} while (0)
#define PUT_SDB_VAL(a) \
do { \
extern FILE *asm_out_text_file; \
fputs ("\t.val\t", asm_out_text_file); \
output_addr_const (asm_out_text_file, (a)); \
fputc (';', asm_out_text_file); \
} while (0)
#define PUT_SDB_DEF(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t%s.def\t", \
(TARGET_GAS) ? "" : "#"); \
ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
fputc (';', asm_out_text_file); \
} while (0)
#define PUT_SDB_PLAIN_DEF(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
(TARGET_GAS) ? "" : "#", (a)); \
} while (0)
#define PUT_SDB_ENDEF \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t.endef\n"); \
} while (0)
#define PUT_SDB_TYPE(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
} while (0)
#define PUT_SDB_SIZE(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t.size\t"); \
fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
fprintf (asm_out_text_file, ";"); \
} while (0)
#define PUT_SDB_DIM(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
} while (0)
#ifndef PUT_SDB_START_DIM
#define PUT_SDB_START_DIM \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t.dim\t"); \
} while (0)
#endif
#ifndef PUT_SDB_NEXT_DIM
#define PUT_SDB_NEXT_DIM(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "%d,", a); \
} while (0)
#endif
#ifndef PUT_SDB_LAST_DIM
#define PUT_SDB_LAST_DIM(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "%d;", a); \
} while (0)
#endif
#define PUT_SDB_TAG(a) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, "\t.tag\t"); \
ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
fputc (';', asm_out_text_file); \
} while (0)
#define PUT_SDB_BLOCK_START(LINE) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, \
"%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
LOCAL_LABEL_PREFIX, \
sdb_label_count, \
(TARGET_GAS) ? "" : "#", \
LOCAL_LABEL_PREFIX, \
sdb_label_count, \
(LINE)); \
sdb_label_count++; \
} while (0)
#define PUT_SDB_BLOCK_END(LINE) \
do { \
extern FILE *asm_out_text_file; \
fprintf (asm_out_text_file, \
"%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
LOCAL_LABEL_PREFIX, \
sdb_label_count, \
(TARGET_GAS) ? "" : "#", \
LOCAL_LABEL_PREFIX, \
sdb_label_count, \
(LINE)); \
sdb_label_count++; \
} while (0)
#define PUT_SDB_FUNCTION_START(LINE)
#define PUT_SDB_FUNCTION_END(LINE) \
do { \
extern FILE *asm_out_text_file; \
ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
} while (0)
#define PUT_SDB_EPILOGUE_END(NAME)
#define PUT_SDB_SRC_FILE(FILENAME) \
do { \
extern FILE *asm_out_text_file; \
output_file_directive (asm_out_text_file, (FILENAME));\
} while (0)
#define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
sprintf ((BUFFER), ".%dfake", (NUMBER));
#define DEBUGGER_AUTO_OFFSET(X) \
mips_debugger_offset (X, (HOST_WIDE_INT) 0)
#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
#define OBJECT_FORMAT_COFF
#define EXTENDED_COFF
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
#if !defined(MIPSEL) && !defined(__MIPSEL__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif
#define MAX_BITS_PER_WORD 64
#define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
#define MIN_UNITS_PER_WORD 4
#define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
#define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
#define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
#define UNITS_PER_FPVALUE \
(TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
#define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
#ifndef MAX_WCHAR_TYPE_SIZE
#ifndef WCHAR_TYPE_SIZE
#define MAX_WCHAR_TYPE_SIZE 64
#endif
#endif
#define SHORT_TYPE_SIZE 16
#define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
#define MAX_LONG_TYPE_SIZE 64
#define LONG_LONG_TYPE_SIZE 64
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE \
(mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
#define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
#ifdef IN_LIBGCC2
#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
|| (defined _ABI64 && _MIPS_SIM == _ABI64)
# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
# else
# define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
# endif
#endif
#ifndef POINTER_SIZE
#define POINTER_SIZE (Pmode == DImode ? 64 : 32)
#endif
#define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
#define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
|| mips_abi == ABI_64 \
|| (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
#define FUNCTION_BOUNDARY 32
#define EMPTY_FIELD_BOUNDARY 32
#define STRUCTURE_SIZE_BOUNDARY 8
#define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
#define STRICT_ALIGNMENT 1
#define PCC_BITFIELD_TYPE_MATTERS 1
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
#undef DATA_ALIGNMENT
#define DATA_ALIGNMENT(TYPE, ALIGN) \
((((ALIGN) < BITS_PER_WORD) \
&& (TREE_CODE (TYPE) == ARRAY_TYPE \
|| TREE_CODE (TYPE) == UNION_TYPE \
|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
#define PAD_VARARGS_DOWN (TARGET_64BIT \
|| mips_abi == ABI_MEABI \
? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
#define PROMOTE_PROTOTYPES 1
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE) \
(TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
? SIGN_EXTEND : ZERO_EXTEND)
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
(MODE) = SImode;
#define PROMOTE_FUNCTION_ARGS
#define PROMOTE_FUNCTION_RETURN
#define FIRST_PSEUDO_REGISTER 176
#define FIXED_REGISTERS \
{ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
#define CALL_USED_REGISTERS \
{ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
#define CALL_REALLY_USED_REGISTERS \
{ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
\
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
}
#define GP_REG_FIRST 0
#define GP_REG_LAST 31
#define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
#define GP_DBX_FIRST 0
#define FP_REG_FIRST 32
#define FP_REG_LAST 63
#define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
#define MD_REG_FIRST 64
#define MD_REG_LAST 66
#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
#define ST_REG_FIRST 67
#define ST_REG_LAST 74
#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
#define RAP_REG_NUM 75
#define COP0_REG_FIRST 80
#define COP0_REG_LAST 111
#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
#define COP2_REG_FIRST 112
#define COP2_REG_LAST 143
#define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
#define COP3_REG_FIRST 144
#define COP3_REG_LAST 175
#define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
#define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
#define AT_REGNUM (GP_REG_FIRST + 1)
#define HI_REGNUM (MD_REG_FIRST + 0)
#define LO_REGNUM (MD_REG_FIRST + 1)
#define HILO_REGNUM (MD_REG_FIRST + 2)
#define FPSW_REGNUM ST_REG_FIRST
#define GP_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
#define M16_REG_P(REGNO) \
(((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
#define FP_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
#define MD_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
#define ST_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
#define COP0_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
#define COP2_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
#define COP3_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
#define ALL_COP_REG_P(REGNO) \
((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
(COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
: COP3_REG_P (REGNO) ? '3' : '?')
#define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
#define MODES_TIEABLE_P(MODE1, MODE2) \
((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
== (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
#define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
#define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
#define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
#define HARD_FRAME_POINTER_REGNUM \
(TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
#define ARG_POINTER_REGNUM GP_REG_FIRST
#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
#define STRUCT_VALUE 0
#define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
#define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
#define NO_FUNCTION_CSE 1
#define NO_RECURSIVE_FUNCTION_CSE 1
#define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
#define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
enum reg_class
{
NO_REGS,
M16_NA_REGS,
M16_REGS,
T_REG,
M16_T_REGS,
GR_REGS,
FP_REGS,
HI_REG,
LO_REG,
HILO_REG,
MD_REGS,
COP0_REGS,
COP2_REGS,
COP3_REGS,
HI_AND_GR_REGS,
LO_AND_GR_REGS,
HILO_AND_GR_REGS,
HI_AND_FP_REGS,
COP0_AND_GR_REGS,
COP2_AND_GR_REGS,
COP3_AND_GR_REGS,
ALL_COP_REGS,
ALL_COP_AND_GR_REGS,
ST_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define GENERAL_REGS GR_REGS
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"M16_NA_REGS", \
"M16_REGS", \
"T_REG", \
"M16_T_REGS", \
"GR_REGS", \
"FP_REGS", \
"HI_REG", \
"LO_REG", \
"HILO_REG", \
"MD_REGS", \
\
"COP0_REGS", \
"COP2_REGS", \
"COP3_REGS", \
"HI_AND_GR_REGS", \
"LO_AND_GR_REGS", \
"HILO_AND_GR_REGS", \
"HI_AND_FP_REGS", \
"COP0_AND_GR_REGS", \
"COP2_AND_GR_REGS", \
"COP3_AND_GR_REGS", \
"ALL_COP_REGS", \
"ALL_COP_AND_GR_REGS", \
"ST_REGS", \
"ALL_REGS" \
}
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
{ 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
{ 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
{ 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, \
{ 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } \
}
extern const enum reg_class mips_regno_to_class[];
#define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
#define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
#define INDEX_REG_CLASS NO_REGS
#define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
#define GR_REG_CLASS_P(CLASS) \
((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
|| (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
#define COP_REG_CLASS_P(CLASS) \
((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
#define REG_ALLOC_ORDER \
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
}
#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
extern enum reg_class mips_char_to_class[256];
#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
: (C) == 'J' ? ((VALUE) == 0) \
: (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
: (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
&& (((VALUE) & ~2147483647) == 0 \
|| ((VALUE) & ~2147483647) == ~2147483647)) \
: (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
&& (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
&& (((VALUE) & 0x0000ffff) != 0 \
|| (((VALUE) & ~2147483647) != 0 \
&& ((VALUE) & ~2147483647) != ~2147483647))) \
: (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
: (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
: (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
: 0)
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' \
&& (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
#define EXTRA_CONSTRAINT(OP,CODE) \
(((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
: ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
&& mips16_gp_offset_p (OP)) \
: (GET_CODE (OP) != MEM) ? FALSE \
: ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
: FALSE)
#define PREFERRED_RELOAD_CLASS(X,CLASS) \
((CLASS) != ALL_REGS \
? (! TARGET_MIPS16 \
? (CLASS) \
: ((CLASS) != GR_REGS \
? (CLASS) \
: M16_REGS)) \
: ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
|| GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
? (TARGET_SOFT_FLOAT \
? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
: FP_REGS) \
: ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
|| GET_MODE (X) == VOIDmode) \
? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
: (CLASS))))
#if 0
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
((!TARGET_DEBUG_H_MODE \
&& GET_MODE_CLASS (MODE) == MODE_INT \
&& ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
|| (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
|| (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
&& ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
|| (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
#endif
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
mips_secondary_reload_class (CLASS, MODE, X, 1)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
mips_secondary_reload_class (CLASS, MODE, X, 0)
#define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
mips_cannot_change_mode_class (FROM, TO, CLASS)
#define STACK_GROWS_DOWNWARD
#define STARTING_FRAME_OFFSET \
(current_function_outgoing_args_size \
+ (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
#if 0
#define STACK_DYNAMIC_OFFSET(FUNDECL) \
((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
? 4*UNITS_PER_WORD \
: current_function_outgoing_args_size)
#endif
#define RETURN_ADDR_RTX(count, frame) \
(((count) == 0) \
? (leaf_function_p () \
? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
: gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
RETURN_ADDRESS_POINTER_REGNUM))) \
: (rtx) 0)
#define MASK_RETURN_ADDR GEN_INT (-2)
#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
{ ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
{ RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
{ RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
{ FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
#define CAN_ELIMINATE(FROM, TO) \
(((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
&& (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
|| (TO) == HARD_FRAME_POINTER_REGNUM)) \
|| ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
&& ((TO) == HARD_FRAME_POINTER_REGNUM \
|| ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
&& ! (TARGET_MIPS16 && TARGET_64BIT) \
&& (! TARGET_MIPS16 \
|| compute_frame_size (get_frame_size ()) < 32768)))))
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
(OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
#define ACCUMULATE_OUTGOING_ARGS 1
#if 0
#define FIRST_PARM_OFFSET(FNDECL) \
(FNDECL != 0 \
&& TREE_TYPE (FNDECL) != 0 \
&& TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
&& (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
|| TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
? UNITS_PER_WORD \
: 0)
#else
#define FIRST_PARM_OFFSET(FNDECL) 0
#endif
#define REG_PARM_STACK_SPACE(FNDECL) \
((mips_abi == ABI_32 || mips_abi == ABI_O64) \
? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
: 0)
#define OUTGOING_REG_PARM_STACK_SPACE
#define STACK_BOUNDARY \
((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
? 64 : 128)
#ifndef STACK_ARGS_ADJUST
#define STACK_ARGS_ADJUST(SIZE) \
{ \
if (SIZE.constant < 4 * UNITS_PER_WORD) \
SIZE.constant = 4 * UNITS_PER_WORD; \
}
#endif
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
#define GP_RETURN (GP_REG_FIRST + 2)
#define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
#define MAX_ARGS_IN_REGISTERS \
((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
#define BIGGEST_MAX_ARGS_IN_REGISTERS 8
#define GP_ARG_FIRST (GP_REG_FIRST + 4)
#define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
#define FP_ARG_FIRST (FP_REG_FIRST + 12)
#define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
#define LIBCALL_VALUE(MODE) \
mips_function_value (NULL_TREE, NULL, (MODE))
#define FUNCTION_VALUE(VALTYPE, FUNC) \
mips_function_value ((VALTYPE), (FUNC), VOIDmode)
#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
|| (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
&& (N) == FP_RETURN + 2))
#define FUNCTION_ARG_REGNO_P(N) \
((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
|| (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
&& ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
&& !fixed_regs[N])
#define RETURN_IN_MEMORY(TYPE) \
mips_return_in_memory (TYPE)
#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
(PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
(TYPE), (NO_RTL))
#define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
typedef struct mips_args {
int gp_reg_found;
unsigned int arg_number;
unsigned int num_gprs;
unsigned int num_fprs;
unsigned int stack_words;
int fp_code;
int prototype;
unsigned int num_adjusts;
rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
function_arg_advance (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg( &CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
(((TYPE) != 0) \
? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
? PARM_BOUNDARY \
: TYPE_ALIGN(TYPE)) \
: ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
? PARM_BOUNDARY \
: GET_MODE_ALIGNMENT(MODE)))
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
#define FUNCTION_ARG_PADDING(MODE, TYPE) \
(! BYTES_BIG_ENDIAN \
? upward \
: (((MODE) == BLKmode \
? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
&& int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
: (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
&& (mips_abi == ABI_32 \
|| mips_abi == ABI_O64 \
|| mips_abi == ABI_EABI \
|| GET_MODE_CLASS (MODE) == MODE_INT))) \
? downward : upward))
#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
(mips_abi == ABI_EABI && (NAMED) \
&& FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
#define MUST_PASS_IN_STACK(MODE,TYPE) \
((TYPE) != 0 \
&& (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
|| TREE_ADDRESSABLE (TYPE) \
|| ((MODE) == BLKmode \
&& mips_abi != ABI_32 && mips_abi != ABI_O64 \
&& ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
&& 0 == (int_size_in_bytes (TYPE) \
% (PARM_BOUNDARY / BITS_PER_UNIT))) \
&& (FUNCTION_ARG_PADDING (MODE, TYPE) \
== (BYTES_BIG_ENDIAN ? upward : downward)))))
#define EABI_FLOAT_VARARGS_P \
(mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
#define MUST_SAVE_REGISTER(regno) \
((regs_ever_live[regno] && !call_used_regs[regno]) \
|| (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
|| (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
#define MIPS_STACK_ALIGN(LOC) \
((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
? ((LOC) + 7) & ~7 \
: ((LOC) + 15) & ~15)
#define BUILD_VA_LIST_TYPE(VALIST) \
(VALIST) = mips_build_va_list ()
#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
mips_va_start (valist, nextarg)
#define EXPAND_BUILTIN_VA_ARG(valist, type) \
mips_va_arg (valist, type)
#define FUNCTION_PROFILER(FILE, LABELNO) \
{ \
if (TARGET_MIPS16) \
sorry ("mips16 function profiling"); \
fprintf (FILE, "\t.set\tnoat\n"); \
fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
fprintf (FILE, \
"\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
TARGET_64BIT ? "dsubu" : "subu", \
reg_names[STACK_POINTER_REGNUM], \
reg_names[STACK_POINTER_REGNUM], \
Pmode == DImode ? 16 : 8); \
fprintf (FILE, "\tjal\t_mcount\n"); \
fprintf (FILE, "\t.set\tat\n"); \
}
#define EXIT_IGNORE_STACK 1
#define TRAMPOLINE_TEMPLATE(STREAM) \
{ \
fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
if (Pmode == DImode) \
{ \
fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
} \
else \
{ \
fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
} \
fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
if (Pmode == DImode) \
{ \
fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
} \
else \
{ \
fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
} \
}
#define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
#define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
#ifndef CACHE_FLUSH_FUNC
#define CACHE_FLUSH_FUNC "_flush_cache"
#endif
#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
{ \
rtx addr = ADDR; \
if (Pmode == DImode) \
{ \
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
} \
else \
{ \
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
} \
\
\
\
if (mips_cache_flush_func && mips_cache_flush_func[0]) \
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
0, VOIDmode, 3, addr, Pmode, \
GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
GEN_INT (3), TYPE_MODE (integer_type_node)); \
}
#define BASE_REG_P(regno, mode) \
(TARGET_MIPS16 \
? (M16_REG_P (regno) \
|| (regno) == FRAME_POINTER_REGNUM \
|| (regno) == ARG_POINTER_REGNUM \
|| ((regno) == STACK_POINTER_REGNUM \
&& (GET_MODE_SIZE (mode) == 4 \
|| GET_MODE_SIZE (mode) == 8))) \
: GP_REG_P (regno))
#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
(mode))
#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
(((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
#define REGNO_OK_FOR_INDEX_P(regno) 0
#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
#ifndef REG_OK_STRICT
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
mips_reg_mode_ok_for_base_p (X, MODE, 0)
#else
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
mips_reg_mode_ok_for_base_p (X, MODE, 1)
#endif
#define REG_OK_FOR_INDEX_P(X) 0
#define MAX_REGS_PER_ADDRESS 1
#if 1
#define GO_PRINTF(x) fprintf(stderr, (x))
#define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
#define GO_DEBUG_RTX(x) debug_rtx(x)
#else
#define GO_PRINTF(x)
#define GO_PRINTF2(x,y)
#define GO_DEBUG_RTX(x)
#endif
#ifdef REG_OK_STRICT
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
if (mips_legitimate_address_p (MODE, X, 1)) \
goto ADDR; \
}
#else
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
{ \
if (mips_legitimate_address_p (MODE, X, 0)) \
goto ADDR; \
}
#endif
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST \
&& ! (flag_pic && pic_address_needs_scratch (X)) \
&& (TARGET_GAS) \
&& (mips_abi != ABI_N32 \
&& mips_abi != ABI_64)))
#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
#define LEGITIMATE_CONSTANT_P(X) \
((GET_CODE (X) != CONST_DOUBLE \
|| mips_const_double_ok (X, GET_MODE (X))) \
&& ! (GET_CODE (X) == CONST \
&& ! TARGET_GAS \
&& (mips_abi == ABI_N32 \
|| mips_abi == ABI_64)) \
&& (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
{ \
register rtx xinsn = (X); \
\
if (TARGET_DEBUG_B_MODE) \
{ \
GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
GO_DEBUG_RTX (xinsn); \
} \
\
if (mips_split_addresses && mips_check_split (X, MODE)) \
{ \
\
X = gen_rtx_LO_SUM (Pmode, \
copy_to_mode_reg (Pmode, \
gen_rtx (HIGH, Pmode, X)), \
X); \
goto WIN; \
} \
\
if (GET_CODE (xinsn) == CONST \
&& ((flag_pic && pic_address_needs_scratch (xinsn)) \
\
|| (!TARGET_GAS \
&& (mips_abi == ABI_N32 \
|| mips_abi == ABI_64)))) \
{ \
rtx ptr_reg = gen_reg_rtx (Pmode); \
rtx constant = XEXP (XEXP (xinsn, 0), 1); \
\
emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
\
X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
if (SMALL_INT (constant)) \
goto WIN; \
\
xinsn = X; \
} \
\
if (GET_CODE (xinsn) == PLUS) \
{ \
register rtx xplus0 = XEXP (xinsn, 0); \
register rtx xplus1 = XEXP (xinsn, 1); \
register enum rtx_code code0 = GET_CODE (xplus0); \
register enum rtx_code code1 = GET_CODE (xplus1); \
\
if (code0 != REG && code1 == REG) \
{ \
xplus0 = XEXP (xinsn, 1); \
xplus1 = XEXP (xinsn, 0); \
code0 = GET_CODE (xplus0); \
code1 = GET_CODE (xplus1); \
} \
\
if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
&& code1 == CONST_INT && !SMALL_INT (xplus1)) \
{ \
rtx int_reg = gen_reg_rtx (Pmode); \
rtx ptr_reg = gen_reg_rtx (Pmode); \
\
emit_move_insn (int_reg, \
GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
\
emit_insn (gen_rtx_SET (VOIDmode, \
ptr_reg, \
gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
\
X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
goto WIN; \
} \
} \
\
if (TARGET_DEBUG_B_MODE) \
GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
}
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
#define ASM_OUTPUT_LABELREF(FILE,NAME) \
if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
asm_fprintf ((FILE), "%U%s", \
XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
else \
asm_fprintf ((FILE), "%U%s", (NAME))
#define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
#define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
mips_string_length = 0;
#if 0
#define CONSTANT_AFTER_FUNCTION_P(tree) \
(TARGET_MIPS16 && mips16_constant_after_function_p (tree))
#endif
#define CASE_VECTOR_MODE \
(TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
#define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
#ifndef DEFAULT_SIGNED_CHAR
#define DEFAULT_SIGNED_CHAR 1
#endif
#define MOVE_MAX (TARGET_64BIT ? 8 : 4)
#define MAX_MOVE_MAX 8
#define SLOW_BYTE_ACCESS 1
#define STORE_FLAG_VALUE 1
#define SHIFT_COUNT_TRUNCATED 1
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
(TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
#ifndef Pmode
#define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
#endif
#define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
#define CONST_COSTS(X,CODE,OUTER_CODE) \
case CONST_INT: \
if (! TARGET_MIPS16) \
{ \
\
return 0; \
} \
if ((OUTER_CODE) == SET) \
{ \
if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
return 0; \
else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
|| (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
return COSTS_N_INSNS (1); \
else \
return COSTS_N_INSNS (2); \
} \
\
if ((OUTER_CODE) == PLUS \
&& INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
return 0; \
\
if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
|| (OUTER_CODE) == LSHIFTRT) \
{ \
if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
return 0; \
return COSTS_N_INSNS (1); \
} \
\
if ((OUTER_CODE) == XOR \
&& INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
return 0; \
\
if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
|| (OUTER_CODE) == GE || (OUTER_CODE) == GT \
|| (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
|| (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
&& INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
return 0; \
\
if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
&& INTVAL (X) == 0) \
return 0; \
\
\
if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
return COSTS_N_INSNS (1); \
else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
|| (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
return COSTS_N_INSNS (2); \
else \
return COSTS_N_INSNS (3); \
\
case LABEL_REF: \
return COSTS_N_INSNS (2); \
\
case CONST: \
{ \
rtx offset = const0_rtx; \
rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
\
if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
{ \
\
if ((OUTER_CODE) == PLUS) \
return 0; \
else if ((OUTER_CODE) == SET) \
return COSTS_N_INSNS (1); \
else \
return COSTS_N_INSNS (2); \
} \
\
if (GET_CODE (symref) == LABEL_REF) \
return COSTS_N_INSNS (2); \
\
if (GET_CODE (symref) != SYMBOL_REF) \
return COSTS_N_INSNS (4); \
\
\
if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
return COSTS_N_INSNS (2); \
\
return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
} \
\
case SYMBOL_REF: \
return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
\
case CONST_DOUBLE: \
{ \
rtx high, low; \
if (TARGET_MIPS16) \
return COSTS_N_INSNS (4); \
split_double (X, &high, &low); \
return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
|| low == CONST0_RTX (GET_MODE (low))) \
? 2 : 4); \
}
#define RTX_COSTS(X,CODE,OUTER_CODE) \
case MEM: \
{ \
int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
if (simple_memory_operand (X, GET_MODE (X))) \
return COSTS_N_INSNS (num_words); \
\
return COSTS_N_INSNS (2*num_words); \
} \
\
case FFS: \
return COSTS_N_INSNS (6); \
\
case NOT: \
return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
\
case AND: \
case IOR: \
case XOR: \
if (GET_MODE (X) == DImode && !TARGET_64BIT) \
return COSTS_N_INSNS (2); \
\
break; \
\
case ASHIFT: \
case ASHIFTRT: \
case LSHIFTRT: \
if (GET_MODE (X) == DImode && !TARGET_64BIT) \
return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
\
break; \
\
case ABS: \
{ \
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode || xmode == DFmode) \
return COSTS_N_INSNS (1); \
\
return COSTS_N_INSNS (4); \
} \
\
case PLUS: \
case MINUS: \
{ \
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode || xmode == DFmode) \
{ \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (2); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (3); \
else \
return COSTS_N_INSNS (6); \
} \
\
if (xmode == DImode && !TARGET_64BIT) \
return COSTS_N_INSNS (4); \
\
break; \
} \
\
case NEG: \
if (GET_MODE (X) == DImode && !TARGET_64BIT) \
return 4; \
\
break; \
\
case MULT: \
{ \
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900 \
|| TUNE_MIPS5000) \
return COSTS_N_INSNS (4); \
else if (TUNE_MIPS6000 \
|| TUNE_MIPS5400 \
|| TUNE_MIPS5500) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (7); \
} \
\
if (xmode == DFmode) \
{ \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900 \
|| TUNE_MIPS5000) \
return COSTS_N_INSNS (5); \
else if (TUNE_MIPS6000 \
|| TUNE_MIPS5400 \
|| TUNE_MIPS5500) \
return COSTS_N_INSNS (6); \
else \
return COSTS_N_INSNS (8); \
} \
\
if (TUNE_MIPS3000) \
return COSTS_N_INSNS (12); \
else if (TUNE_MIPS3900) \
return COSTS_N_INSNS (2); \
else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
return COSTS_N_INSNS ((xmode == DImode) ? 4 : 3); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (17); \
else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (10); \
} \
\
case DIV: \
case MOD: \
{ \
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (12); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (15); \
else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
return COSTS_N_INSNS (30); \
else \
return COSTS_N_INSNS (23); \
} \
\
if (xmode == DFmode) \
{ \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (19); \
else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
return COSTS_N_INSNS (59); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (16); \
else \
return COSTS_N_INSNS (36); \
} \
} \
\
\
case UDIV: \
case UMOD: \
if (TUNE_MIPS3000 \
|| TUNE_MIPS3900) \
return COSTS_N_INSNS (35); \
else if (TUNE_MIPS6000) \
return COSTS_N_INSNS (38); \
else if (TUNE_MIPS5000) \
return COSTS_N_INSNS (36); \
else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
return COSTS_N_INSNS ((GET_MODE (X) == SImode) ? 42 : 74); \
else \
return COSTS_N_INSNS (69); \
\
case SIGN_EXTEND: \
\
if (TARGET_64BIT && GET_MODE (X) == DImode \
&& GET_MODE (XEXP (X, 0)) == SImode) \
return COSTS_N_INSNS (1); \
else \
return COSTS_N_INSNS (2); \
\
case ZERO_EXTEND: \
if (TARGET_64BIT && GET_MODE (X) == DImode \
&& GET_MODE (XEXP (X, 0)) == SImode) \
return COSTS_N_INSNS (2); \
else \
return COSTS_N_INSNS (1);
#define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
mips_register_move_cost (MODE, FROM, TO)
#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
(((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
+ memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
#define AVOID_CCMODE_COPIES
#define BRANCH_COST \
((! TARGET_MIPS16 \
&& (TUNE_MIPS4000 || TUNE_MIPS6000)) \
? 2 : 1)
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
#define PREDICATE_CODES \
{"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
{"arith_operand", { REG, CONST_INT, SUBREG }}, \
{"arith32_operand", { REG, CONST_INT, SUBREG }}, \
{"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
{"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
{"small_int", { CONST_INT }}, \
{"large_int", { CONST_INT }}, \
{"mips_const_double_ok", { CONST_DOUBLE }}, \
{"const_float_1_operand", { CONST_DOUBLE }}, \
{"simple_memory_operand", { MEM, SUBREG }}, \
{"equality_op", { EQ, NE }}, \
{"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
LTU, LEU }}, \
{"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
{"pc_or_label_operand", { PC, LABEL_REF }}, \
{"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
{"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, \
REG, MEM}}, \
{"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, REG, \
MEM, SIGN_EXTEND }}, \
{"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
{"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
SIGN_EXTEND }}, \
{"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
SIGN_EXTEND }}, \
{"se_arith_operand", { REG, CONST_INT, SUBREG, \
SIGN_EXTEND }}, \
{"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, \
REG, SIGN_EXTEND }}, \
{"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
CONST_DOUBLE, CONST }}, \
{"fcc_register_operand", { REG, SUBREG }}, \
{"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
{"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
#define SPECIAL_MODE_PREDICATES \
"pc_or_label_operand",
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
final_prescan_insn (INSN, OPVEC, NOPERANDS)
#undef ASM_FILE_START
#define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
#ifndef ASM_APP_ON
#define ASM_APP_ON " #APP\n"
#endif
#ifndef ASM_APP_OFF
#define ASM_APP_OFF " #NO_APP\n"
#endif
#define REGISTER_NAMES \
{ \
&mips_reg_names[ 0][0], \
&mips_reg_names[ 1][0], \
&mips_reg_names[ 2][0], \
&mips_reg_names[ 3][0], \
&mips_reg_names[ 4][0], \
&mips_reg_names[ 5][0], \
&mips_reg_names[ 6][0], \
&mips_reg_names[ 7][0], \
&mips_reg_names[ 8][0], \
&mips_reg_names[ 9][0], \
&mips_reg_names[10][0], \
&mips_reg_names[11][0], \
&mips_reg_names[12][0], \
&mips_reg_names[13][0], \
&mips_reg_names[14][0], \
&mips_reg_names[15][0], \
&mips_reg_names[16][0], \
&mips_reg_names[17][0], \
&mips_reg_names[18][0], \
&mips_reg_names[19][0], \
&mips_reg_names[20][0], \
&mips_reg_names[21][0], \
&mips_reg_names[22][0], \
&mips_reg_names[23][0], \
&mips_reg_names[24][0], \
&mips_reg_names[25][0], \
&mips_reg_names[26][0], \
&mips_reg_names[27][0], \
&mips_reg_names[28][0], \
&mips_reg_names[29][0], \
&mips_reg_names[30][0], \
&mips_reg_names[31][0], \
&mips_reg_names[32][0], \
&mips_reg_names[33][0], \
&mips_reg_names[34][0], \
&mips_reg_names[35][0], \
&mips_reg_names[36][0], \
&mips_reg_names[37][0], \
&mips_reg_names[38][0], \
&mips_reg_names[39][0], \
&mips_reg_names[40][0], \
&mips_reg_names[41][0], \
&mips_reg_names[42][0], \
&mips_reg_names[43][0], \
&mips_reg_names[44][0], \
&mips_reg_names[45][0], \
&mips_reg_names[46][0], \
&mips_reg_names[47][0], \
&mips_reg_names[48][0], \
&mips_reg_names[49][0], \
&mips_reg_names[50][0], \
&mips_reg_names[51][0], \
&mips_reg_names[52][0], \
&mips_reg_names[53][0], \
&mips_reg_names[54][0], \
&mips_reg_names[55][0], \
&mips_reg_names[56][0], \
&mips_reg_names[57][0], \
&mips_reg_names[58][0], \
&mips_reg_names[59][0], \
&mips_reg_names[60][0], \
&mips_reg_names[61][0], \
&mips_reg_names[62][0], \
&mips_reg_names[63][0], \
&mips_reg_names[64][0], \
&mips_reg_names[65][0], \
&mips_reg_names[66][0], \
&mips_reg_names[67][0], \
&mips_reg_names[68][0], \
&mips_reg_names[69][0], \
&mips_reg_names[70][0], \
&mips_reg_names[71][0], \
&mips_reg_names[72][0], \
&mips_reg_names[73][0], \
&mips_reg_names[74][0], \
&mips_reg_names[75][0], \
&mips_reg_names[76][0], \
&mips_reg_names[77][0], \
&mips_reg_names[78][0], \
&mips_reg_names[79][0], \
&mips_reg_names[80][0], \
&mips_reg_names[81][0], \
&mips_reg_names[82][0], \
&mips_reg_names[83][0], \
&mips_reg_names[84][0], \
&mips_reg_names[85][0], \
&mips_reg_names[86][0], \
&mips_reg_names[87][0], \
&mips_reg_names[88][0], \
&mips_reg_names[89][0], \
&mips_reg_names[90][0], \
&mips_reg_names[91][0], \
&mips_reg_names[92][0], \
&mips_reg_names[93][0], \
&mips_reg_names[94][0], \
&mips_reg_names[95][0], \
&mips_reg_names[96][0], \
&mips_reg_names[97][0], \
&mips_reg_names[98][0], \
&mips_reg_names[99][0], \
&mips_reg_names[100][0], \
&mips_reg_names[101][0], \
&mips_reg_names[102][0], \
&mips_reg_names[103][0], \
&mips_reg_names[104][0], \
&mips_reg_names[105][0], \
&mips_reg_names[106][0], \
&mips_reg_names[107][0], \
&mips_reg_names[108][0], \
&mips_reg_names[109][0], \
&mips_reg_names[110][0], \
&mips_reg_names[111][0], \
&mips_reg_names[112][0], \
&mips_reg_names[113][0], \
&mips_reg_names[114][0], \
&mips_reg_names[115][0], \
&mips_reg_names[116][0], \
&mips_reg_names[117][0], \
&mips_reg_names[118][0], \
&mips_reg_names[119][0], \
&mips_reg_names[120][0], \
&mips_reg_names[121][0], \
&mips_reg_names[122][0], \
&mips_reg_names[123][0], \
&mips_reg_names[124][0], \
&mips_reg_names[125][0], \
&mips_reg_names[126][0], \
&mips_reg_names[127][0], \
&mips_reg_names[128][0], \
&mips_reg_names[129][0], \
&mips_reg_names[130][0], \
&mips_reg_names[131][0], \
&mips_reg_names[132][0], \
&mips_reg_names[133][0], \
&mips_reg_names[134][0], \
&mips_reg_names[135][0], \
&mips_reg_names[136][0], \
&mips_reg_names[137][0], \
&mips_reg_names[138][0], \
&mips_reg_names[139][0], \
&mips_reg_names[140][0], \
&mips_reg_names[141][0], \
&mips_reg_names[142][0], \
&mips_reg_names[143][0], \
&mips_reg_names[144][0], \
&mips_reg_names[145][0], \
&mips_reg_names[146][0], \
&mips_reg_names[147][0], \
&mips_reg_names[148][0], \
&mips_reg_names[149][0], \
&mips_reg_names[150][0], \
&mips_reg_names[151][0], \
&mips_reg_names[152][0], \
&mips_reg_names[153][0], \
&mips_reg_names[154][0], \
&mips_reg_names[155][0], \
&mips_reg_names[156][0], \
&mips_reg_names[157][0], \
&mips_reg_names[158][0], \
&mips_reg_names[159][0], \
&mips_reg_names[160][0], \
&mips_reg_names[161][0], \
&mips_reg_names[162][0], \
&mips_reg_names[163][0], \
&mips_reg_names[164][0], \
&mips_reg_names[165][0], \
&mips_reg_names[166][0], \
&mips_reg_names[167][0], \
&mips_reg_names[168][0], \
&mips_reg_names[169][0], \
&mips_reg_names[170][0], \
&mips_reg_names[171][0], \
&mips_reg_names[172][0], \
&mips_reg_names[173][0], \
&mips_reg_names[174][0], \
&mips_reg_names[175][0] \
}
#define DEBUG_REGISTER_NAMES \
{ \
"$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
"t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
"hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
"$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
"$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
"$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
"$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
"$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
"$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
"$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
"$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
"$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
"$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
"$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
}
#define ADDITIONAL_REGISTER_NAMES \
{ \
{ "$0", 0 + GP_REG_FIRST }, \
{ "$1", 1 + GP_REG_FIRST }, \
{ "$2", 2 + GP_REG_FIRST }, \
{ "$3", 3 + GP_REG_FIRST }, \
{ "$4", 4 + GP_REG_FIRST }, \
{ "$5", 5 + GP_REG_FIRST }, \
{ "$6", 6 + GP_REG_FIRST }, \
{ "$7", 7 + GP_REG_FIRST }, \
{ "$8", 8 + GP_REG_FIRST }, \
{ "$9", 9 + GP_REG_FIRST }, \
{ "$10", 10 + GP_REG_FIRST }, \
{ "$11", 11 + GP_REG_FIRST }, \
{ "$12", 12 + GP_REG_FIRST }, \
{ "$13", 13 + GP_REG_FIRST }, \
{ "$14", 14 + GP_REG_FIRST }, \
{ "$15", 15 + GP_REG_FIRST }, \
{ "$16", 16 + GP_REG_FIRST }, \
{ "$17", 17 + GP_REG_FIRST }, \
{ "$18", 18 + GP_REG_FIRST }, \
{ "$19", 19 + GP_REG_FIRST }, \
{ "$20", 20 + GP_REG_FIRST }, \
{ "$21", 21 + GP_REG_FIRST }, \
{ "$22", 22 + GP_REG_FIRST }, \
{ "$23", 23 + GP_REG_FIRST }, \
{ "$24", 24 + GP_REG_FIRST }, \
{ "$25", 25 + GP_REG_FIRST }, \
{ "$26", 26 + GP_REG_FIRST }, \
{ "$27", 27 + GP_REG_FIRST }, \
{ "$28", 28 + GP_REG_FIRST }, \
{ "$29", 29 + GP_REG_FIRST }, \
{ "$30", 30 + GP_REG_FIRST }, \
{ "$31", 31 + GP_REG_FIRST }, \
{ "$sp", 29 + GP_REG_FIRST }, \
{ "$fp", 30 + GP_REG_FIRST }, \
{ "at", 1 + GP_REG_FIRST }, \
{ "v0", 2 + GP_REG_FIRST }, \
{ "v1", 3 + GP_REG_FIRST }, \
{ "a0", 4 + GP_REG_FIRST }, \
{ "a1", 5 + GP_REG_FIRST }, \
{ "a2", 6 + GP_REG_FIRST }, \
{ "a3", 7 + GP_REG_FIRST }, \
{ "t0", 8 + GP_REG_FIRST }, \
{ "t1", 9 + GP_REG_FIRST }, \
{ "t2", 10 + GP_REG_FIRST }, \
{ "t3", 11 + GP_REG_FIRST }, \
{ "t4", 12 + GP_REG_FIRST }, \
{ "t5", 13 + GP_REG_FIRST }, \
{ "t6", 14 + GP_REG_FIRST }, \
{ "t7", 15 + GP_REG_FIRST }, \
{ "s0", 16 + GP_REG_FIRST }, \
{ "s1", 17 + GP_REG_FIRST }, \
{ "s2", 18 + GP_REG_FIRST }, \
{ "s3", 19 + GP_REG_FIRST }, \
{ "s4", 20 + GP_REG_FIRST }, \
{ "s5", 21 + GP_REG_FIRST }, \
{ "s6", 22 + GP_REG_FIRST }, \
{ "s7", 23 + GP_REG_FIRST }, \
{ "t8", 24 + GP_REG_FIRST }, \
{ "t9", 25 + GP_REG_FIRST }, \
{ "k0", 26 + GP_REG_FIRST }, \
{ "k1", 27 + GP_REG_FIRST }, \
{ "gp", 28 + GP_REG_FIRST }, \
{ "sp", 29 + GP_REG_FIRST }, \
{ "fp", 30 + GP_REG_FIRST }, \
{ "ra", 31 + GP_REG_FIRST }, \
{ "$sp", 29 + GP_REG_FIRST }, \
{ "$fp", 30 + GP_REG_FIRST } \
ALL_COP_ADDITIONAL_REGISTER_NAMES \
}
#define ALL_COP_ADDITIONAL_REGISTER_NAMES
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
#define DBR_OUTPUT_SEQEND(STREAM) \
do \
{ \
if (set_nomacro > 0 && --set_nomacro == 0) \
fputs ("\t.set\tmacro\n", STREAM); \
\
if (set_noreorder > 0 && --set_noreorder == 0) \
fputs ("\t.set\treorder\n", STREAM); \
\
dslots_jump_filled++; \
fputs ("\n", STREAM); \
} \
while (0)
#ifndef SET_FILE_NUMBER
#define SET_FILE_NUMBER() ++num_source_filenames
#endif
#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
mips_output_filename (STREAM, NAME)
#define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
do \
{ \
fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
output_quoted_string (STREAM, NAME); \
fputs ("\n", STREAM); \
} \
while (0)
#ifndef LABEL_AFTER_LOC
#define LABEL_AFTER_LOC(STREAM)
#endif
#ifndef ASM_OUTPUT_SOURCE_LINE
#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
mips_output_lineno (STREAM, LINE)
#endif
#undef ASM_DECLARE_OBJECT_NAME
#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
do \
{ \
mips_declare_object (STREAM, NAME, "", ":\n", 0); \
} \
while (0)
#define GLOBAL_ASM_OP "\t.globl\t"
#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
do { \
\
if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
&& TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
&& (DECL_INITIAL (DECL) == 0 \
|| DECL_INITIAL (DECL) == error_mark_node)) \
{ \
if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
(*targetm.asm_out.globalize_label) (STREAM, NAME); \
\
readonly_data_section (); \
ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
(SIZE)); \
} \
else \
mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
(SIZE)); \
} while (0)
#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
#define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
mips_output_external(STREAM,DECL,NAME)
#undef ASM_FILE_END
#define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
#undef TEXT_SECTION
#define TEXT_SECTION() \
do { \
extern FILE *asm_out_text_file; \
if (TARGET_FILE_SWITCHING) \
asm_out_file = asm_out_text_file; \
fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
fputc ('\n', asm_out_file); \
} while (0)
#undef ASM_DECLARE_FUNCTION_NAME
#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
#undef ASM_OUTPUT_INTERNAL_LABEL
#define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
#undef ASM_GENERATE_INTERNAL_LABEL
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
fprintf (STREAM, "\t%s\t%sL%d\n", \
Pmode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, \
VALUE)
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
do { \
if (TARGET_MIPS16) \
fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
else if (TARGET_EMBEDDED_PIC) \
fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
Pmode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
fprintf (STREAM, "\t%s\t%sL%d\n", \
Pmode == DImode ? ".gpdword" : ".gpword", \
LOCAL_LABEL_PREFIX, VALUE); \
else \
fprintf (STREAM, "\t%s\t%sL%d\n", \
Pmode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, VALUE); \
} while (0)
#undef ASM_OUTPUT_CASE_LABEL
#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
do { \
if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
function_section (current_function_decl); \
ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
} while (0)
#define ASM_OUTPUT_ALIGN(STREAM,LOG) \
fprintf (STREAM, "\t.align\t%d\n", (LOG))
#undef ASM_OUTPUT_SKIP
#define ASM_OUTPUT_SKIP(STREAM,SIZE) \
fprintf (STREAM, "\t.space\t%u\n", (SIZE))
#undef ASM_OUTPUT_ASCII
#define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
mips_output_ascii (STREAM, STRING, LEN)
#undef ASM_OUTPUT_IDENT
#define ASM_OUTPUT_IDENT(FILE, STRING) \
{ \
const char *p = STRING; \
int size = strlen (p) + 1; \
readonly_data_section (); \
assemble_string (p, size); \
}
#ifndef MIPS_DEFAULT_GVALUE
#define MIPS_DEFAULT_GVALUE 8
#endif
#define TEXT_SECTION_ASM_OP "\t.text"
#define DATA_SECTION_ASM_OP "\t.data"
#define SDATA_SECTION_ASM_OP "\t.sdata"
#undef READONLY_DATA_SECTION_ASM_OP
#define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
#define SMALL_DATA_SECTION sdata_section
#undef EXTRA_SECTIONS
#define EXTRA_SECTIONS in_sdata
#undef EXTRA_SECTION_FUNCTIONS
#define EXTRA_SECTION_FUNCTIONS \
void \
sdata_section () \
{ \
if (in_section != in_sdata) \
{ \
fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
in_section = in_sdata; \
} \
}
#undef TARGET_ASM_SELECT_SECTION
#define TARGET_ASM_SELECT_SECTION mips_select_section
#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
#define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
do \
{ \
fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
TARGET_64BIT ? "dsubu" : "subu", \
reg_names[STACK_POINTER_REGNUM], \
reg_names[STACK_POINTER_REGNUM], \
TARGET_64BIT ? "sd" : "sw", \
reg_names[REGNO], \
reg_names[STACK_POINTER_REGNUM]); \
} \
while (0)
#define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
do \
{ \
if (! set_noreorder) \
fprintf (STREAM, "\t.set\tnoreorder\n"); \
\
dslots_load_total++; \
dslots_load_filled++; \
fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
TARGET_64BIT ? "ld" : "lw", \
reg_names[REGNO], \
reg_names[STACK_POINTER_REGNUM], \
TARGET_64BIT ? "daddu" : "addu", \
reg_names[STACK_POINTER_REGNUM], \
reg_names[STACK_POINTER_REGNUM]); \
\
if (! set_noreorder) \
fprintf (STREAM, "\t.set\treorder\n"); \
} \
while (0)
#ifndef ASM_COMMENT_START
#define ASM_COMMENT_START " #"
#endif
#define CODE_MASK 0x8F300
#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
#undef SIZE_TYPE
#define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
&& mips_abi != ABI_32 \
&& mips_abi != ABI_O64)
#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
#ifndef INIT_SUBTARGET_OPTABS
#define INIT_SUBTARGET_OPTABS
#endif
#define INIT_TARGET_OPTABS \
do \
{ \
if (! TARGET_MIPS16 || ! mips16_hard_float) \
INIT_SUBTARGET_OPTABS; \
else \
{ \
add_optab->handlers[(int) SFmode].libfunc = \
init_one_libfunc ("__mips16_addsf3"); \
sub_optab->handlers[(int) SFmode].libfunc = \
init_one_libfunc ("__mips16_subsf3"); \
smul_optab->handlers[(int) SFmode].libfunc = \
init_one_libfunc ("__mips16_mulsf3"); \
sdiv_optab->handlers[(int) SFmode].libfunc = \
init_one_libfunc ("__mips16_divsf3"); \
\
eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
\
floatsisf_libfunc = \
init_one_libfunc ("__mips16_floatsisf"); \
fixsfsi_libfunc = \
init_one_libfunc ("__mips16_fixsfsi"); \
\
if (TARGET_DOUBLE_FLOAT) \
{ \
add_optab->handlers[(int) DFmode].libfunc = \
init_one_libfunc ("__mips16_adddf3"); \
sub_optab->handlers[(int) DFmode].libfunc = \
init_one_libfunc ("__mips16_subdf3"); \
smul_optab->handlers[(int) DFmode].libfunc = \
init_one_libfunc ("__mips16_muldf3"); \
sdiv_optab->handlers[(int) DFmode].libfunc = \
init_one_libfunc ("__mips16_divdf3"); \
\
extendsfdf2_libfunc = \
init_one_libfunc ("__mips16_extendsfdf2"); \
truncdfsf2_libfunc = \
init_one_libfunc ("__mips16_truncdfsf2"); \
\
eqdf2_libfunc = \
init_one_libfunc ("__mips16_eqdf2"); \
nedf2_libfunc = \
init_one_libfunc ("__mips16_nedf2"); \
gtdf2_libfunc = \
init_one_libfunc ("__mips16_gtdf2"); \
gedf2_libfunc = \
init_one_libfunc ("__mips16_gedf2"); \
ltdf2_libfunc = \
init_one_libfunc ("__mips16_ltdf2"); \
ledf2_libfunc = \
init_one_libfunc ("__mips16_ledf2"); \
\
floatsidf_libfunc = \
init_one_libfunc ("__mips16_floatsidf"); \
fixdfsi_libfunc = \
init_one_libfunc ("__mips16_fixdfsi"); \
} \
} \
} \
while (0)
#define DFMODE_NAN \
unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
#define SFMODE_NAN \
unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
#define TARGET_MEM_FUNCTIONS
#ifndef __mips16
#if _MIPS_SIM == _MIPS_SIM_ABI32
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n\
.set noreorder\n\
bal 1f\n\
nop\n\
1: .cpload $31\n\
.set reorder\n\
jal " USER_LABEL_PREFIX #FUNC "\n\
" TEXT_SECTION_ASM_OP);
#endif
#if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
|| (defined _ABI64 && _MIPS_SIM == _ABI64)
#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
asm (SECTION_OP "\n\
.set noreorder\n\
bal 1f\n\
nop\n\
1: .set reorder\n\
.cpsetup $31, $2, 1b\n\
jal " USER_LABEL_PREFIX #FUNC "\n\
" TEXT_SECTION_ASM_OP);
#endif
#endif