AllocationOrder.cpp [plain text]
#include "AllocationOrder.h"
#include "VirtRegMap.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
using namespace llvm;
AllocationOrder::AllocationOrder(unsigned VirtReg,
const VirtRegMap &VRM,
const RegisterClassInfo &RegClassInfo)
: Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
std::pair<unsigned, unsigned> HintPair =
VRM.getRegInfo().getRegAllocationHint(VirtReg);
const MachineRegisterInfo &MRI = VRM.getRegInfo();
Hint = HintPair.second;
if (TargetRegisterInfo::isVirtualRegister(Hint))
Hint = VRM.getPhys(Hint);
if (HintPair.first) {
const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
ArrayRef<uint16_t> Order =
TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
VRM.getMachineFunction());
if (Order.empty())
return;
OwnedBegin = true;
unsigned *P = new unsigned[Order.size()];
Begin = P;
for (unsigned i = 0; i != Order.size(); ++i)
if (!MRI.isReserved(Order[i]))
*P++ = Order[i];
End = P;
Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint,
VRM.getMachineFunction());
} else {
ArrayRef<unsigned> O = RCI.getOrder(RC);
Begin = O.begin();
End = O.end();
}
if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
!RC->contains(Hint) || MRI.isReserved(Hint)))
Hint = 0;
}
AllocationOrder::~AllocationOrder() {
if (OwnedBegin)
delete [] Begin;
}