LLVMTargetMachine.cpp [plain text]
#include "llvm/Target/TargetMachine.h"
#include "llvm/PassManager.h"
#include "llvm/Pass.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Analysis/LoopPass.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetAsmInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
namespace llvm {
bool EnableFastISel;
}
static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
cl::desc("Print LLVM IR input to isel pass"));
static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
cl::desc("Dump emitter generated instructions as assembly"));
static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
cl::desc("Dump garbage collector data"));
static cl::opt<bool>
DisablePostRAScheduler("disable-post-RA-scheduler",
cl::desc("Disable scheduling after register allocation"),
cl::init(true));
static cl::opt<cl::boolOrDefault>
EnableFastISelOption("fast-isel", cl::Hidden,
cl::desc("Enable the experimental \"fast\" instruction selector"));
FileModel::Model
LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
raw_ostream &Out,
CodeGenFileType FileType,
CodeGenOpt::Level OptLevel) {
if (addCommonCodeGenPasses(PM, OptLevel))
return FileModel::Error;
PM.add(createDebugLabelFoldingPass());
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
if (OptLevel != CodeGenOpt::None)
PM.add(createCodePlacementOptPass());
switch (FileType) {
default:
break;
case TargetMachine::AssemblyFile:
if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
return FileModel::Error;
return FileModel::AsmFile;
case TargetMachine::ObjectFile:
if (getMachOWriterInfo())
return FileModel::MachOFile;
else if (getELFWriterInfo())
return FileModel::ElfFile;
}
return FileModel::Error;
}
bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
MachineCodeEmitter *MCE,
CodeGenOpt::Level OptLevel) {
if (MCE)
addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
PM.add(createGCInfoDeleter());
PM.add(createMachineCodeDeleter());
return false; }
bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
MachineCodeEmitter &MCE,
CodeGenOpt::Level OptLevel) {
if (addCommonCodeGenPasses(PM, OptLevel))
return true;
if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
PM.add(createGCInfoDeleter());
PM.add(createMachineCodeDeleter());
return false; }
bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
if (OptLevel != CodeGenOpt::None) {
PM.add(createLoopStrengthReducePass(getTargetLowering()));
if (PrintLSR)
PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
}
PM.add(createGCLoweringPass());
if (!getTargetAsmInfo()->doesSupportExceptionHandling())
PM.add(createLowerInvokePass(getTargetLowering()));
PM.add(createUnreachableBlockEliminationPass());
if (OptLevel != CodeGenOpt::None)
PM.add(createCodeGenPreparePass(getTargetLowering()));
PM.add(createStackProtectorPass(getTargetLowering()));
if (PrintISelInput)
PM.add(createPrintFunctionPass("\n\n"
"*** Final LLVM Code input to ISel ***\n",
&errs()));
if (EnableFastISelOption == cl::BOU_TRUE ||
(OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
EnableFastISel = true;
if (addInstSelector(PM, OptLevel))
return true;
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
if (OptLevel != CodeGenOpt::None) {
PM.add(createMachineLICMPass());
PM.add(createMachineSinkingPass());
}
if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
PM.add(createRegisterAllocator());
if (OptLevel != CodeGenOpt::None)
PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr));
if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
PM.add(createLowerSubregsPass());
if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr));
PM.add(createPrologEpilogCodeInserter());
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
PM.add(createPostRAScheduler());
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
}
if (OptLevel != CodeGenOpt::None)
PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
PM.add(createGCMachineCodeAnalysisPass());
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(cerr));
if (PrintGCInfo)
PM.add(createGCInfoPrinter(*cerr));
return false;
}