#ifndef ARMSUBTARGET_H
#define ARMSUBTARGET_H
#include "llvm/Target/TargetInstrItineraries.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtarget.h"
#include "ARMBaseRegisterInfo.h"
#include <string>
namespace llvm {
class GlobalValue;
class ARMSubtarget : public TargetSubtarget {
protected:
enum ARMArchEnum {
V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
};
enum ARMProcFamilyEnum {
Others, CortexA8, CortexA9
};
enum ARMFPEnum {
None, VFPv2, VFPv3, NEON
};
enum ThumbTypeEnum {
Thumb1,
Thumb2
};
ARMArchEnum ARMArchVersion;
ARMProcFamilyEnum ARMProcFamily;
ARMFPEnum ARMFPUType;
bool UseNEONForSinglePrecisionFP;
bool SlowVMLx;
bool SlowFPBrcc;
bool IsThumb;
ThumbTypeEnum ThumbMode;
bool NoARM;
bool PostRAScheduler;
bool IsR9Reserved;
bool UseMovt;
bool HasFP16;
bool HasD16;
bool HasHardwareDivide;
bool HasT2ExtractPack;
bool HasDataBarrier;
bool Pref32BitThumb;
bool FPOnlySP;
bool AllowsUnalignedMem;
unsigned stackAlignment;
std::string CPUString;
InstrItineraryData InstrItins;
public:
enum {
isELF, isDarwin
} TargetType;
enum {
ARM_ABI_APCS,
ARM_ABI_AAPCS } TargetABI;
ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
unsigned getMaxInlineSizeThreshold() const {
return isThumb1Only() ? 0 : 64;
}
std::string ParseSubtargetFeatures(const std::string &FS,
const std::string &CPU);
bool hasV4TOps() const { return ARMArchVersion >= V4T; }
bool hasV5TOps() const { return ARMArchVersion >= V5T; }
bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
bool hasV6Ops() const { return ARMArchVersion >= V6; }
bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
bool hasV7Ops() const { return ARMArchVersion >= V7A; }
bool isCortexA8() const { return ARMProcFamily == CortexA8; }
bool isCortexA9() const { return ARMProcFamily == CortexA9; }
bool hasARMOps() const { return !NoARM; }
bool hasVFP2() const { return ARMFPUType >= VFPv2; }
bool hasVFP3() const { return ARMFPUType >= VFPv3; }
bool hasNEON() const { return ARMFPUType >= NEON; }
bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; }
bool hasDivide() const { return HasHardwareDivide; }
bool hasT2ExtractPack() const { return HasT2ExtractPack; }
bool hasDataBarrier() const { return HasDataBarrier; }
bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
bool isFPBrccSlow() const { return SlowFPBrcc; }
bool isFPOnlySP() const { return FPOnlySP; }
bool prefers32BitThumb() const { return Pref32BitThumb; }
bool hasFP16() const { return HasFP16; }
bool hasD16() const { return HasD16; }
bool isTargetDarwin() const { return TargetType == isDarwin; }
bool isTargetELF() const { return TargetType == isELF; }
bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
bool isThumb() const { return IsThumb; }
bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
bool hasThumb2() const { return ThumbMode >= Thumb2; }
bool isR9Reserved() const { return IsR9Reserved; }
bool useMovt() const { return UseMovt && hasV6T2Ops(); }
bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
const std::string & getCPUString() const { return CPUString; }
unsigned getMispredictionPenalty() const;
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
unsigned getStackAlignment() const { return stackAlignment; }
bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
};
}
#endif // ARMSUBTARGET_H