#include <stdio.h>
#include "sysdep.h"
#include "opcode/arc.h"
#include "opintl.h"
#ifndef NULL
#define NULL 0
#endif
#define INSERT_FN(fn) \
static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
int, const struct arc_operand_value *, long, \
const char **))
#define EXTRACT_FN(fn) \
static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
int, const struct arc_operand_value **, int *))
INSERT_FN (insert_reg);
INSERT_FN (insert_shimmfinish);
INSERT_FN (insert_limmfinish);
INSERT_FN (insert_shimmoffset);
INSERT_FN (insert_shimmzero);
INSERT_FN (insert_flag);
INSERT_FN (insert_flagfinish);
INSERT_FN (insert_cond);
INSERT_FN (insert_forcelimm);
INSERT_FN (insert_reladdr);
INSERT_FN (insert_absaddr);
INSERT_FN (insert_unopmacro);
EXTRACT_FN (extract_reg);
EXTRACT_FN (extract_flag);
EXTRACT_FN (extract_cond);
EXTRACT_FN (extract_reladdr);
EXTRACT_FN (extract_unopmacro);
const struct arc_operand arc_operands[] =
{
#define UNUSED 0
{ 0 },
#define REGA (UNUSED + 1)
{ 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
#define REGB (REGA + 1)
{ 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
#define REGC (REGB + 1)
{ 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
#define SHIMMFINISH (REGC + 1)
{ 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
#define LIMMFINISH (SHIMMFINISH + 1)
{ 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
#define SHIMMOFFSET (LIMMFINISH + 1)
{ 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 },
#define SHIMMZERO (SHIMMOFFSET + 1)
{ '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 },
#define FLAG (SHIMMZERO + 1)
{ 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
#define FLAGFINISH (FLAG + 1)
{ 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
#define FLAGINSN (FLAGFINISH + 1)
{ 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
#define DELAY (FLAGINSN + 1)
{ 'n', 2, 5, ARC_OPERAND_SUFFIX },
#define COND (DELAY + 1)
{ 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
#define FORCELIMM (COND + 1)
{ 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm },
#define BRANCH (FORCELIMM + 1)
{ 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
#define JUMP (BRANCH + 1)
{ 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr },
#define SIZE1 (JUMP + 1)
{ 'z', 2, 1, ARC_OPERAND_SUFFIX },
#define SIZE10 (SIZE1 + 1)
{ 'Z', 2, 10, ARC_OPERAND_SUFFIX, },
#define SIZE22 (SIZE10 + 1)
{ 'y', 2, 22, ARC_OPERAND_SUFFIX, },
#define SIGN0 (SIZE22 + 1)
{ 'x', 1, 0, ARC_OPERAND_SUFFIX },
#define SIGN9 (SIGN0 + 1)
{ 'X', 1, 9, ARC_OPERAND_SUFFIX },
#define ADDRESS3 (SIGN9 + 1)
{ 'w', 1, 3, ARC_OPERAND_SUFFIX },
#define ADDRESS12 (ADDRESS3 + 1)
{ 'W', 1, 12, ARC_OPERAND_SUFFIX },
#define ADDRESS24 (ADDRESS12 + 1)
{ 'v', 1, 24, ARC_OPERAND_SUFFIX },
#define CACHEBYPASS5 (ADDRESS24 + 1)
{ 'e', 1, 5, ARC_OPERAND_SUFFIX },
#define CACHEBYPASS14 (CACHEBYPASS5 + 1)
{ 'E', 1, 14, ARC_OPERAND_SUFFIX },
#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
{ 'D', 1, 26, ARC_OPERAND_SUFFIX },
#define UNOPMACRO (CACHEBYPASS26 + 1)
{ 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
#define MODDOT (UNOPMACRO + 1)
{ '.', 1, 0, ARC_MOD_DOT },
#define REG (MODDOT + 1)
{ 'r', 6, 0, ARC_MOD_REG },
#define AUXREG (REG + 1)
{ 'A', 9, 0, ARC_MOD_AUXREG },
{ 0 }
};
unsigned char arc_operand_map[256] = { 0 };
#define I(x) (((x) & 31) << 27)
#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
#define R(x,b,m) (((x) & (m)) << (b))
struct arc_opcode arc_opcodes[] = {
{ "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) },
{ "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
{ "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
{ "nop", 0xffffffff, 0x7fffffff },
{ "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
{ "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) },
{ "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) },
{ "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) },
{ "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) },
{ "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) },
{ "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH },
{ "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH },
{ "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) },
{ "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) },
{ "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) },
{ "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) },
{ "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) },
{ "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) },
{ "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
{ "lp%q%.n %B", I(-1), I(6), },
{ "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) },
{ "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) },
{ "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) },
{ "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) },
{ "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) },
{ "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) },
{ "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) },
{ "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) },
{ "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
{ "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) },
{ "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) },
{ "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) },
{ "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) }
};
const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
const struct arc_operand_value arc_reg_names[] =
{
{ "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG },
{ "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG },
{ "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG },
{ "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG },
{ "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG },
{ "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG },
{ "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG },
{ "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG },
{ "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG },
{ "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG },
{ "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG },
{ "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG },
{ "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG },
{ "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG },
{ "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG },
{ "lp_count", 60, REG },
{ "r27", 27, REG }, { "r28", 28, REG },
{ "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG },
{ "status", 0, AUXREG },
{ "semaphore", 1, AUXREG },
{ "lp_start", 2, AUXREG },
{ "lp_end", 3, AUXREG },
{ "identity", 4, AUXREG },
{ "debug", 5, AUXREG },
};
const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
const struct arc_operand_value arc_suffixes[] =
{
{ "", 0, -1 },
{ "al", 0, COND },
{ "ra", 0, COND },
{ "eq", 1, COND },
{ "z", 1, COND },
{ "ne", 2, COND },
{ "nz", 2, COND },
{ "p", 3, COND },
{ "pl", 3, COND },
{ "n", 4, COND },
{ "mi", 4, COND },
{ "c", 5, COND },
{ "cs", 5, COND },
{ "lo", 5, COND },
{ "nc", 6, COND },
{ "cc", 6, COND },
{ "hs", 6, COND },
{ "v", 7, COND },
{ "vs", 7, COND },
{ "nv", 8, COND },
{ "vc", 8, COND },
{ "gt", 9, COND },
{ "ge", 10, COND },
{ "lt", 11, COND },
{ "le", 12, COND },
{ "hi", 13, COND },
{ "ls", 14, COND },
{ "pnz", 15, COND },
{ "f", 1, FLAG },
{ "nd", ARC_DELAY_NONE, DELAY },
{ "d", ARC_DELAY_NORMAL, DELAY },
{ "jd", ARC_DELAY_JUMP, DELAY },
{ "b", 1, SIZE1 },
{ "b", 1, SIZE10 },
{ "b", 1, SIZE22 },
{ "w", 2, SIZE1 },
{ "w", 2, SIZE10 },
{ "w", 2, SIZE22 },
{ "x", 1, SIGN0 },
{ "x", 1, SIGN9 },
{ "a", 1, ADDRESS3 },
{ "a", 1, ADDRESS12 },
{ "a", 1, ADDRESS24 },
{ "di", 1, CACHEBYPASS5 },
{ "di", 1, CACHEBYPASS14 },
{ "di", 1, CACHEBYPASS26 },
};
const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
static struct arc_opcode *opcode_map[26 + 1];
static struct arc_opcode *icode_map[32];
static int cpu_type;
int
arc_get_opcode_mach (bfd_mach, big_p)
int bfd_mach, big_p;
{
static int mach_type_map[] =
{
ARC_MACH_BASE
};
return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0);
}
void
arc_opcode_init_tables (flags)
int flags;
{
static int init_p = 0;
cpu_type = flags;
if (!init_p)
{
register int i,n;
memset (arc_operand_map, 0, sizeof (arc_operand_map));
n = sizeof (arc_operands) / sizeof (arc_operands[0]);
for (i = 0; i < n; ++i)
arc_operand_map[arc_operands[i].fmt] = i;
memset (opcode_map, 0, sizeof (opcode_map));
memset (icode_map, 0, sizeof (icode_map));
for (i = arc_opcodes_count - 1; i >= 0; --i)
{
int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
arc_opcodes[i].next_asm = opcode_map[opcode_hash];
opcode_map[opcode_hash] = &arc_opcodes[i];
arc_opcodes[i].next_dis = icode_map[icode_hash];
icode_map[icode_hash] = &arc_opcodes[i];
}
init_p = 1;
}
}
int
arc_opcode_supported (opcode)
const struct arc_opcode *opcode;
{
if (ARC_OPCODE_CPU (opcode->flags) == 0)
return 1;
if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type))
return 1;
return 0;
}
int
arc_opval_supported (opval)
const struct arc_operand_value *opval;
{
if (ARC_OPVAL_CPU (opval->flags) == 0)
return 1;
if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type))
return 1;
return 0;
}
const struct arc_opcode *
arc_opcode_lookup_asm (insn)
const char *insn;
{
return opcode_map[ARC_HASH_OPCODE (insn)];
}
const struct arc_opcode *
arc_opcode_lookup_dis (insn)
unsigned int insn;
{
return icode_map[ARC_HASH_ICODE (insn)];
}
static int flag_p;
static int flagshimm_handled_p;
static int cond_p;
static int shimm_p;
static int shimm;
static int limm_p;
static long limm;
void
arc_opcode_init_insert ()
{
flag_p = 0;
flagshimm_handled_p = 0;
cond_p = 0;
shimm_p = 0;
limm_p = 0;
}
int
arc_opcode_limm_p (limmp)
long *limmp;
{
if (limmp)
*limmp = limm;
return limm_p;
}
static arc_insn
insert_reg (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
static char buf[100];
if (reg == NULL)
{
if (ARC_SHIMM_CONST_P (value)
&& !cond_p
&& (!shimm_p || shimm == value))
{
int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
flagshimm_handled_p = 1;
shimm_p = 1;
shimm = value;
insn |= marker << operand->shift;
}
else if (!limm_p || limm == value)
{
limm_p = 1;
limm = value;
insn |= ARC_REG_LIMM << operand->shift;
}
else
{
*errmsg = _("unable to fit different valued constants into instruction");
}
}
else
{
if (reg->type == AUXREG)
{
if (!(mods & ARC_MOD_AUXREG))
*errmsg = _("auxiliary register not allowed here");
else
{
insn |= ARC_REG_SHIMM << operand->shift;
insn |= reg->value << arc_operands[reg->type].shift;
}
}
else
{
if ((unsigned int) reg->value > 60)
{
sprintf (buf, _("invalid register number `%d'"), reg->value);
*errmsg = buf;
}
else
insn |= reg->value << operand->shift;
}
}
return insn;
}
static arc_insn
insert_flag (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
flag_p = 1;
return insn;
}
static arc_insn
insert_flagfinish (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
if (flag_p && !flagshimm_handled_p)
{
if (shimm_p)
abort ();
flagshimm_handled_p = 1;
insn |= (1 << operand->shift);
}
return insn;
}
static arc_insn
insert_cond (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
cond_p = 1;
insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
return insn;
}
static arc_insn
insert_forcelimm (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
cond_p = 1;
return insn;
}
static arc_insn
insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
long minval, maxval;
static char buf[100];
if (reg != NULL)
{
*errmsg = "register appears where shimm value expected";
}
else
{
if (operand->flags & ARC_OPERAND_SIGNED)
{
minval = -(1 << (operand->bits - 1));
maxval = (1 << (operand->bits - 1)) - 1;
}
else
{
minval = 0;
maxval = (1 << operand->bits) - 1;
}
if (value < minval || value > maxval)
{
sprintf (buf, _("value won't fit in range %ld - %ld"),
minval, maxval);
*errmsg = buf;
}
else
insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
}
return insn;
}
static arc_insn
insert_shimmzero (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
shimm_p = 1;
shimm = 0;
return insn;
}
static arc_insn
insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
if (shimm_p)
insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
return insn;
}
static arc_insn
insert_limmfinish (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
if (limm_p)
;
return insn;
}
static arc_insn
insert_unopmacro (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
return insn;
}
static arc_insn
insert_reladdr (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
if (value & 3)
*errmsg = _("branch address not on 4 byte boundary");
insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
return insn;
}
static arc_insn
insert_absaddr (insn, operand, mods, reg, value, errmsg)
arc_insn insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value *reg;
long value;
const char **errmsg;
{
if (limm_p)
;
return insn;
}
static const struct arc_operand_value *lookup_register (int type, long regno);
void
arc_opcode_init_extract ()
{
flag_p = 0;
flagshimm_handled_p = 0;
shimm_p = 0;
limm_p = 0;
}
static long
extract_reg (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value **opval;
int *invalid;
{
int regno;
long value;
regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
if (regno == ARC_REG_SHIMM)
{
value = insn[0] & 511;
if ((operand->flags & ARC_OPERAND_SIGNED)
&& (value & 256))
value -= 512;
flagshimm_handled_p = 1;
}
else if (regno == ARC_REG_SHIMM_UPDATE)
{
value = insn[0] & 511;
if ((operand->flags & ARC_OPERAND_SIGNED)
&& (value & 256))
value -= 512;
flag_p = 1;
flagshimm_handled_p = 1;
}
else if (regno == ARC_REG_LIMM)
{
value = insn[1];
limm_p = 1;
}
else
{
const struct arc_operand_value *reg = lookup_register (REG, regno);
if (reg == NULL)
abort ();
if (opval != NULL)
*opval = reg;
value = regno;
}
if ((mods & ARC_MOD_AUXREG)
&& ARC_REG_CONSTANT_P (regno))
{
const struct arc_operand_value *reg = lookup_register (AUXREG, value);
if (reg != NULL && opval != NULL)
*opval = reg;
}
return value;
}
static long
extract_flag (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value **opval;
int *invalid;
{
int f;
const struct arc_operand_value *val;
if (flagshimm_handled_p)
f = flag_p != 0;
else
f = (insn[0] & (1 << operand->shift)) != 0;
if (f == 0)
return 0;
val = arc_opcode_lookup_suffix (operand, 1);
if (opval != NULL && val != NULL)
*opval = val;
return val->value;
}
static long
extract_cond (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value **opval;
int *invalid;
{
long cond;
const struct arc_operand_value *val;
if (flagshimm_handled_p)
return 0;
cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
val = arc_opcode_lookup_suffix (operand, cond);
if (opval != NULL && val != NULL)
*opval = val;
return cond;
}
static long
extract_reladdr (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value **opval;
int *invalid;
{
long addr;
addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
if ((operand->flags & ARC_OPERAND_SIGNED)
&& (addr & (1 << (operand->bits - 1))))
addr -= 1 << operand->bits;
return addr << 2;
}
static long
extract_unopmacro (insn, operand, mods, opval, invalid)
arc_insn *insn;
const struct arc_operand *operand;
int mods;
const struct arc_operand_value **opval;
int *invalid;
{
if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
!= ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
if (invalid != NULL)
*invalid = 1;
return 0;
}
const struct arc_operand_value *
arc_opcode_lookup_suffix (type, value)
const struct arc_operand *type;
int value;
{
register const struct arc_operand_value *v,*end;
for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
if (type == &arc_operands[v->type]
&& value == v->value)
return v;
return 0;
}
static const struct arc_operand_value *
lookup_register (type, regno)
int type;
long regno;
{
register const struct arc_operand_value *r,*end;
if (type == REG)
return &arc_reg_names[regno];
for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
r < end; ++r)
if (type == r->type && regno == r->value)
return r;
return 0;
}